diff --git a/src/ARM.cpp b/src/ARM.cpp
index cb72dad5..907a4790 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -1259,6 +1259,31 @@ bool ARMv4::DataWrite32S(u32 addr, u32 val, bool dataabort)
 }
 
 
+void ARMv5::AddCycles_CD()
+{
+    s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
+    s32 numD = DataCycles;
+
+    s32 early;
+    if (DataRegion == Mem9_ITCM)
+    {
+        early = (CodeRegion == Mem9_ITCM) ? -1 : 0;
+    }
+    else if (DataRegion == Mem9_DTCM)
+    {
+        early = 2;
+    }
+    else if (DataRegion == Mem9_MainRAM)
+    {
+        early = (CodeRegion == Mem9_MainRAM) ? 0 : 18; // CHECKME: how early can main ram be?
+    }
+    else early = (DataRegion == CodeRegion) ? 4 : 6;
+    
+    s32 code = numC - early;
+    if (code < 0) code = 0;
+    Cycles += std::max(code + numD, numC);
+}
+
 void ARMv5::AddCycles_CDI()
 {
     // LDR/LDM cycles. ARM9 seems to skip the internal cycle there.
@@ -1269,7 +1294,7 @@ void ARMv5::AddCycles_CDI()
     s32 early;
     switch (DataRegion)
     {
-        case 0: // background region; CHECKME
+        case 0: // background region;
         case Mem9_DTCM:
         case Mem9_BIOS:
         case Mem9_WRAM:
@@ -1297,17 +1322,10 @@ void ARMv5::AddCycles_CDI()
             early = (CodeRegion == Mem9_ITCM) ? -1 : 0;
             break;
     }
-
-    if (numD > early)
-    {
-        numC -= early;
-        if (numC < 0) numC = 0;
-        Cycles += numC + numD;
-    }
-    else
-    {
-        Cycles += numC;
-    }
+    
+    s32 code = numC - early;
+    if (code < 0) code = 0;
+    Cycles += std::max(code + numD, numC);
 }
 
 void ARMv4::AddCycles_C()
diff --git a/src/ARM.h b/src/ARM.h
index 25a96ef2..68eeb685 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -327,17 +327,7 @@ public:
 
     void AddCycles_CDI() override;
 
-    void AddCycles_CD() override
-    {
-        // TODO: ITCM data fetches shouldn't be parallelized, they say
-        s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
-        s32 numD = DataCycles;
-
-        //if (DataRegion != CodeRegion)
-            Cycles += std::max(numC + numD - 6, std::max(numC, numD));
-        //else
-        //    Cycles += numC + numD;
-    }
+    void AddCycles_CD() override;
     
 #ifdef INTERLOCK
     // fetch the value of a register while handling any interlock cycles
diff --git a/src/CP15.cpp b/src/CP15.cpp
index 319ac9c4..06e01e83 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -934,10 +934,9 @@ bool ARMv5::DataWrite8(u32 addr, u8 val)
         return false;
     }
 
-    DataRegion = addr;
-
     if (addr < ITCMSize)
     {
+        DataRegion = Mem9_ITCM;
         DataCycles = 1;
         *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
         NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
@@ -945,12 +944,14 @@ bool ARMv5::DataWrite8(u32 addr, u8 val)
     }
     if ((addr & DTCMMask) == DTCMBase)
     {
+        DataRegion = Mem9_DTCM;
         DataCycles = 1;
         *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
         return true;
     }
 
     BusWrite8(addr, val);
+    DataRegion = NDS.ARM9Regions[addr >> 14];
     DataCycles = MemTimings[addr >> 12][1];
     return true;
 }
@@ -963,12 +964,11 @@ bool ARMv5::DataWrite16(u32 addr, u16 val)
         return false;
     }
 
-    DataRegion = addr;
-
     addr &= ~1;
 
     if (addr < ITCMSize)
     {
+        DataRegion = Mem9_ITCM;
         DataCycles = 1;
         *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
         NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
@@ -976,12 +976,14 @@ bool ARMv5::DataWrite16(u32 addr, u16 val)
     }
     if ((addr & DTCMMask) == DTCMBase)
     {
+        DataRegion = Mem9_DTCM;
         DataCycles = 1;
         *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
         return true;
     }
 
     BusWrite16(addr, val);
+    DataRegion = NDS.ARM9Regions[addr >> 14];
     DataCycles = MemTimings[addr >> 12][1];
     return true;
 }
@@ -994,12 +996,11 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
         return false;
     }
 
-    DataRegion = addr;
-
     addr &= ~3;
 
     if (addr < ITCMSize)
     {
+        DataRegion = Mem9_ITCM;
         DataCycles = 1;
         *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
         NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
@@ -1007,12 +1008,14 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
     }
     if ((addr & DTCMMask) == DTCMBase)
     {
+        DataRegion = Mem9_DTCM;
         DataCycles = 1;
         *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
         return true;
     }
 
     BusWrite32(addr, val);
+    DataRegion = NDS.ARM9Regions[addr >> 14];
     DataCycles = MemTimings[addr >> 12][2];
     return true;
 }