make some progress
This commit is contained in:
Arisotura
parent
a9545fbf32
commit
d2bff7c187
352
src/DMA.cpp
352
src/DMA.cpp
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@ -21,6 +21,7 @@
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#include "DSi.h"
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#include "DMA.h"
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#include "GPU.h"
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#include "DMA_Timings.h"
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@ -94,8 +95,8 @@ void DMA::DoSavestate(Savestate* file)
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file->Var32(&CurDstAddr);
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file->Var32(&RemCount);
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file->Var32(&IterCount);
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file->Var32(&SrcAddrInc);
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file->Var32(&DstAddrInc);
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file->Var32((u32*)&SrcAddrInc);
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file->Var32((u32*)&DstAddrInc);
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file->Var32(&Running);
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file->Bool32(&InProgress);
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@ -182,10 +183,349 @@ void DMA::Start()
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else*/
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Running = 2;
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// safety measure
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MRAMBurstTable = DMATiming::MRAMDummy;
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InProgress = true;
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NDS::StopCPU(CPU, 1<<Num);
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}
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void DMA::CalculateTimings(u32& burststart, u32& unit)
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{
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// DMA timing rules:
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// * for an incrementing address: first access (in burst) is nonseq, following ones are seq, maximum burst length is 118 units
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// * for a fixed/decrementing address: all accesses are nonseq
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// * reads from mainRAM take one less cycle when at the end of a 32-byte block
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u32 src_n, src_s, dst_n, dst_s;
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bool src_mainram, sameregion;
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if (CPU == 0)
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{
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u32 src_id = CurSrcAddr >> 14;
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u32 dst_id = CurDstAddr >> 14;
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if (Cnt & (1<<26)) // 32-bit
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{
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src_n = NDS::ARM9MemTimings[src_id][6];
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src_s = NDS::ARM9MemTimings[src_id][7];
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dst_n = NDS::ARM9MemTimings[dst_id][6];
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dst_s = NDS::ARM9MemTimings[dst_id][7];
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}
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else // 16-bit
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{
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src_n = NDS::ARM9MemTimings[src_id][4];
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src_s = NDS::ARM9MemTimings[src_id][5];
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dst_n = NDS::ARM9MemTimings[dst_id][4];
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dst_s = NDS::ARM9MemTimings[dst_id][5];
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}
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u32 src_rgn = NDS::ARM9Regions[src_id];
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u32 dst_rgn = NDS::ARM9Regions[dst_id];
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src_mainram = (src_rgn == NDS::Mem9_MainRAM);
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sameregion = ((src_rgn & dst_rgn) != 0);
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}
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else
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{
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u32 src_id = CurSrcAddr >> 15;
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u32 dst_id = CurDstAddr >> 15;
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if (Cnt & (1<<26)) // 32-bit
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{
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src_n = NDS::ARM7MemTimings[src_id][2];
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src_s = NDS::ARM7MemTimings[src_id][3];
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dst_n = NDS::ARM7MemTimings[dst_id][2];
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dst_s = NDS::ARM7MemTimings[dst_id][3];
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}
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else // 16-bit
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{
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src_n = NDS::ARM7MemTimings[src_id][0];
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src_s = NDS::ARM7MemTimings[src_id][1];
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dst_n = NDS::ARM7MemTimings[dst_id][0];
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dst_s = NDS::ARM7MemTimings[dst_id][1];
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}
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u32 src_rgn = NDS::ARM7Regions[src_id];
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u32 dst_rgn = NDS::ARM7Regions[dst_id];
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src_mainram = (src_rgn == NDS::Mem7_MainRAM);
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sameregion = ((src_rgn & dst_rgn) != 0);
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}
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//
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}
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u32 DMA::UnitTimings9_16(bool burststart)
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{
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u32 src_id = CurSrcAddr >> 14;
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u32 dst_id = CurDstAddr >> 14;
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u32 src_rgn = NDS::ARM9Regions[src_id];
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u32 dst_rgn = NDS::ARM9Regions[dst_id];
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u32 src_n, src_s, dst_n, dst_s;
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src_n = NDS::ARM9MemTimings[src_id][4];
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src_s = NDS::ARM9MemTimings[src_id][5];
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dst_n = NDS::ARM9MemTimings[dst_id][4];
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dst_s = NDS::ARM9MemTimings[dst_id][5];
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u32 ret = 0;
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if (src_rgn == NDS::Mem9_MainRAM)
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{
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if (dst_rgn == NDS::Mem9_MainRAM)
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return 16;
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if (SrcAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (dst_rgn == NDS::Mem9_GBAROM)
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{
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if (dst_s == 4)
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[1];
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else
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[2];
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}
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else
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[0];
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}
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ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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ret += ((CurSrcAddr & 0x1F) == 0x1E) ? 7 : 8;
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ret += burststart ? dst_n : dst_s;
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return ret;
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}
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}
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else if (dst_rgn == NDS::Mem9_MainRAM)
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{
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if (DstAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (src_rgn == NDS::Mem9_GBAROM)
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{
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if (src_s == 4)
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[1];
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else
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[2];
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}
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else
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[0];
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}
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ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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ret += burststart ? src_n : src_s;
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ret += 7;
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return ret;
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}
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}
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else if (src_rgn & dst_rgn)
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{
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return src_n + dst_n + 1;
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}
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else
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{
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if (burststart)
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return src_n + dst_n;
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else
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return src_s + dst_s;
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}
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#if 0
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if (src_rgn == NDS::Mem9_MainRAM)
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{
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// for main RAM: sequential timings only work with incrementing addresses
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// read bursts have a maximum length of 119 halfwords, then 119 halfwords, then 2 halfwords, and so on
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// (this is probably a hardware glitch)
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if (SrcAddrInc > 0)
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{
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if (burststart || BurstCount >= 240)
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BurstCount = 0;
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// note: one of the cycles of the first unit seems to transfer over to the next unit
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// we approximate this by attributing all the cycles to the first unit
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if (BurstCount == 0 || BurstCount == 119 || BurstCount == 238)
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ret += src_n-1;
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//else if (BurstCount == 1 || BurstCount == 120 || BurstCount == 239)
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// ret += src_s + 1;
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else
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ret += src_s;
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BurstCount++;
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}
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else
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{
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ret += src_n;
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if ((CurSrcAddr & 0x1F) == 0x1E) ret--;
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}
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// main RAM reads can parallelize with writes to another region
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//ret--;
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}
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else if (src_rgn == NDS::Mem9_GBAROM)
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{
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// for GBA ROM: sequential timings always work, except for the last halfword
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// of every 0x20000 byte block
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ret += (burststart || ((CurSrcAddr & 0x1FFFF) == 0x1FFFE)) ? src_n : src_s;
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}
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else
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{
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// for other regions: nonseq/sequential timings are the same
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ret += src_s;
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}
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if (dst_rgn == NDS::Mem9_MainRAM)
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{
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// for main RAM: sequential timings only work with incrementing addresses
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// write bursts have a maximum length of 120 halfwords
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if (DstAddrInc > 0)
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{
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if (burststart || BurstCount >= 120)
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BurstCount = 0;
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ret += (BurstCount == 0) ? dst_n-1 : dst_s;
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BurstCount++;
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}
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else
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{
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ret += dst_n-1;
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}
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}
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else if (dst_rgn == NDS::Mem9_GBAROM)
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{
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// for GBA ROM: sequential timings always work, except for the last halfword
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// of every 0x20000 byte block
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ret += (burststart || ((CurDstAddr & 0x1FFFF) == 0x1FFFE)) ? dst_n : dst_s;
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}
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else
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{
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// for other regions: nonseq/sequential timings are the same
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ret += dst_s;
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}
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#endif
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return ret;
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}
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u32 DMA::UnitTimings9_32(bool burststart)
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{
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u32 src_id = CurSrcAddr >> 14;
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u32 dst_id = CurDstAddr >> 14;
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u32 src_rgn = NDS::ARM9Regions[src_id];
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u32 dst_rgn = NDS::ARM9Regions[dst_id];
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u32 src_n, src_s, dst_n, dst_s;
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src_n = NDS::ARM9MemTimings[src_id][6];
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src_s = NDS::ARM9MemTimings[src_id][7];
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dst_n = NDS::ARM9MemTimings[dst_id][6];
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dst_s = NDS::ARM9MemTimings[dst_id][7];
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if (src_rgn & dst_rgn)
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{
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return src_n + dst_n;
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}
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u32 ret = 0;
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ret=1;
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#if 0
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if (src_rgn == NDS::Mem9_MainRAM)
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{
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// for main RAM: sequential timings only work with incrementing addresses
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// read bursts have a maximum length of 118 words
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if (SrcAddrInc > 0)
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{
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if (burststart || BurstCount >= 118)
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BurstCount = 0;
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ret += (BurstCount == 0) ? src_n : src_s;
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BurstCount++;
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}
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else
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{
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ret += src_n;
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if ((CurSrcAddr & 0x1F) == 0x1C) ret--;
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}
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// main RAM reads can parallelize with writes to another region
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ret--;
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}
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else if (src_rgn == NDS::Mem9_GBAROM)
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{
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// for GBA ROM: sequential timings always work, except for the last halfword
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// of every 0x20000 byte block
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ret += (burststart || ((CurSrcAddr & 0x1FFFF) == 0x1FFFC)) ? src_n : src_s;
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}
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else
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{
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// for other regions: nonseq/sequential timings are the same
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ret += src_s;
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}
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if (dst_rgn == NDS::Mem9_MainRAM)
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{
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// for main RAM: sequential timings only work with incrementing addresses
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// write bursts have a maximum length of 80 words
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if (DstAddrInc > 0)
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{
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if (burststart || BurstCount >= 80)
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BurstCount = 0;
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ret += (BurstCount == 0) ? dst_n : dst_s;
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BurstCount++;
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}
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else
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{
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ret += dst_n;
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}
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}
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else if (dst_rgn == NDS::Mem9_GBAROM)
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{
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// for GBA ROM: sequential timings always work, except for the last halfword
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// of every 0x20000 byte block
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ret += (burststart || ((CurDstAddr & 0x1FFFF) == 0x1FFFC)) ? dst_n : dst_s;
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}
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else
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{
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// for other regions: nonseq/sequential timings are the same
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ret += dst_s;
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}
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#endif
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return ret;
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}
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template <int ConsoleType>
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void DMA::Run9()
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{
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@ -224,7 +564,9 @@ void DMA::Run9()
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while (IterCount > 0 && !Stall)
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{
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NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
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//NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
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NDS::ARM9Timestamp += (UnitTimings9_16(burststart) << NDS::ARM9ClockShift);
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burststart = false;
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if (ConsoleType == 1)
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DSi::ARM9Write16(CurDstAddr, DSi::ARM9Read16(CurSrcAddr));
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@ -284,7 +626,9 @@ void DMA::Run9()
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while (IterCount > 0 && !Stall)
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{
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NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
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//NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
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NDS::ARM9Timestamp += (UnitTimings9_32(burststart) << NDS::ARM9ClockShift);
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burststart = false;
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if (ConsoleType == 1)
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DSi::ARM9Write32(CurDstAddr, DSi::ARM9Read32(CurSrcAddr));
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12
src/DMA.h
12
src/DMA.h
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@ -34,6 +34,11 @@ public:
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void WriteCnt(u32 val);
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void Start();
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void CalculateTimings(u32& burststart, u32& unit);
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u32 UnitTimings9_16(bool burststart);
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u32 UnitTimings9_32(bool burststart);
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template <int ConsoleType>
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void Run();
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@ -78,8 +83,8 @@ private:
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u32 CurDstAddr;
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u32 RemCount;
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u32 IterCount;
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u32 SrcAddrInc;
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u32 DstAddrInc;
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s32 SrcAddrInc;
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s32 DstAddrInc;
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u32 CountMask;
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u32 Running;
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@ -89,6 +94,9 @@ private:
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bool Stall;
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bool IsGXFIFODMA;
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u32 MRAMBurstCount;
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u8* MRAMBurstTable;
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};
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#endif
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@ -43,7 +43,9 @@ namespace DMATiming
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// setting. Timings are such that the nonseq setting only matters for the first
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// access, and minor edge cases (like the last of a 0x20000-byte block).
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u8 MRAMRead16Bursts[][] =
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u8 MRAMDummy[1] = {0};
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u8 MRAMRead16Bursts[][256] =
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{
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// main RAM to regular 16bit or 32bit bus (similar)
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{7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
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@ -117,7 +119,7 @@ u8 MRAMRead16Bursts[][] =
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0},
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};
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u8 MRAMRead32Bursts[][] =
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u8 MRAMRead32Bursts[][256] =
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{
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// main RAM to regular 16bit bus
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{9, 4, 3, 3, 3, 3, 3, 3, 3, 3,
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@ -176,7 +178,7 @@ u8 MRAMRead32Bursts[][] =
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0},
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};
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u8 MRAMWrite16Bursts[][] =
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u8 MRAMWrite16Bursts[][256] =
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{
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// regular 16bit or 32bit bus to main RAM (similar)
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{8, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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@ -207,7 +209,7 @@ u8 MRAMWrite16Bursts[][] =
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0},
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};
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u8 MRAMWrite32Bursts[][] =
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u8 MRAMWrite32Bursts[][256] =
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{
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// regular 16bit bus to main RAM
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{9, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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@ -236,7 +238,7 @@ u8 MRAMWrite32Bursts[][] =
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{16, 14, 14, 14, 14, 14, 14, 14, 14, 14,
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14, 14, 14, 14, 14, 14, 14, 14,
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0},
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}
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};
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}
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