From c5258d6377f72053be136254a92b19c96065167e Mon Sep 17 00:00:00 2001
From: Jaklyy <102590697+Jaklyy@users.noreply.github.com>
Date: Mon, 17 Jun 2024 18:07:53 -0400
Subject: [PATCH] verify interlocks for alu and load/store

remove some checks for interlock that im pretty sure can't trigger
---
 src/ARMInterpreter_ALU.cpp       | 38 ++++++++++++++++----------------
 src/ARMInterpreter_LoadStore.cpp | 32 +++++++++++++--------------
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/src/ARMInterpreter_ALU.cpp b/src/ARMInterpreter_ALU.cpp
index 92c027f3..be0498e1 100644
--- a/src/ARMInterpreter_ALU.cpp
+++ b/src/ARMInterpreter_ALU.cpp
@@ -1180,7 +1180,7 @@ void A_QDSUB(ARM* cpu)
 
 
 
-void T_LSL_IMM(ARM* cpu) // verify interlock
+void T_LSL_IMM(ARM* cpu)
 {
     u32 op = cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
     u32 s = (cpu->CurInstr >> 6) & 0x1F;
@@ -1191,7 +1191,7 @@ void T_LSL_IMM(ARM* cpu) // verify interlock
     cpu->AddCycles_C();
 }
 
-void T_LSR_IMM(ARM* cpu) // verify interlock
+void T_LSR_IMM(ARM* cpu)
 {
     u32 op = cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
     u32 s = (cpu->CurInstr >> 6) & 0x1F;
@@ -1202,7 +1202,7 @@ void T_LSR_IMM(ARM* cpu) // verify interlock
     cpu->AddCycles_C();
 }
 
-void T_ASR_IMM(ARM* cpu) // verify interlock
+void T_ASR_IMM(ARM* cpu)
 {
     u32 op = cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
     u32 s = (cpu->CurInstr >> 6) & 0x1F;
@@ -1239,7 +1239,7 @@ void T_SUB_REG_(ARM* cpu)
     cpu->AddCycles_C();
 }
 
-void T_ADD_IMM_(ARM* cpu) // verify interlock
+void T_ADD_IMM_(ARM* cpu)
 {
     u32 a = cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
     u32 b = (cpu->CurInstr >> 6) & 0x7;
@@ -1252,7 +1252,7 @@ void T_ADD_IMM_(ARM* cpu) // verify interlock
     cpu->AddCycles_C();
 }
 
-void T_SUB_IMM_(ARM* cpu) // verify interlock
+void T_SUB_IMM_(ARM* cpu)
 {
     u32 a = cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
     u32 b = (cpu->CurInstr >> 6) & 0x7;
@@ -1265,7 +1265,7 @@ void T_SUB_IMM_(ARM* cpu) // verify interlock
     cpu->AddCycles_C();
 }
 
-void T_MOV_IMM(ARM* cpu) // verify interlock
+void T_MOV_IMM(ARM* cpu)
 {
     u32 b = cpu->CurInstr & 0xFF;
     cpu->R[(cpu->CurInstr >> 8) & 0x7] = b;
@@ -1274,9 +1274,9 @@ void T_MOV_IMM(ARM* cpu) // verify interlock
     cpu->AddCycles_C();
 }
 
-void T_CMP_IMM(ARM* cpu) // verify interlock
+void T_CMP_IMM(ARM* cpu) 
 {
-    u32 a = cpu->R[(cpu->CurInstr >> 8) & 0x7];
+    u32 a = cpu->GetReg((cpu->CurInstr >> 8) & 0x7);
     u32 b = cpu->CurInstr & 0xFF;
     u32 res = a - b;
     cpu->SetNZCV(res & 0x80000000,
@@ -1286,7 +1286,7 @@ void T_CMP_IMM(ARM* cpu) // verify interlock
     cpu->AddCycles_C();
 }
 
-void T_ADD_IMM(ARM* cpu) // verify interlock
+void T_ADD_IMM(ARM* cpu)
 {
     u32 a = cpu->GetReg((cpu->CurInstr >> 8) & 0x7);
     u32 b = cpu->CurInstr & 0xFF;
@@ -1299,7 +1299,7 @@ void T_ADD_IMM(ARM* cpu) // verify interlock
     cpu->AddCycles_C();
 }
 
-void T_SUB_IMM(ARM* cpu) // verify interlock
+void T_SUB_IMM(ARM* cpu)
 {
     u32 a = cpu->GetReg((cpu->CurInstr >> 8) & 0x7);
     u32 b = cpu->CurInstr & 0xFF;
@@ -1516,7 +1516,7 @@ void T_MVN_REG(ARM* cpu)
 // TODO: check those when MSBs and MSBd are cleared
 // GBAtek says it's not allowed, but it works atleast on the ARM9
 
-void T_ADD_HIREG(ARM* cpu) // verify interlock
+void T_ADD_HIREG(ARM* cpu)
 {
     u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8);
     u32 rs = (cpu->CurInstr >> 3) & 0xF;
@@ -1536,7 +1536,7 @@ void T_ADD_HIREG(ARM* cpu) // verify interlock
     }
 }
 
-void T_CMP_HIREG(ARM* cpu) // verify interlock
+void T_CMP_HIREG(ARM* cpu)
 {
     u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8);
     u32 rs = (cpu->CurInstr >> 3) & 0xF;
@@ -1552,7 +1552,7 @@ void T_CMP_HIREG(ARM* cpu) // verify interlock
     cpu->AddCycles_C();
 }
 
-void T_MOV_HIREG(ARM* cpu) // verify interlock
+void T_MOV_HIREG(ARM* cpu)
 {
     u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8);
     u32 rs = (cpu->CurInstr >> 3) & 0xF;
@@ -1582,25 +1582,25 @@ void T_MOV_HIREG(ARM* cpu) // verify interlock
 }
 
 
-void T_ADD_PCREL(ARM* cpu) // verify interlock
+void T_ADD_PCREL(ARM* cpu) // checkme: pc shouldn't be able to interlock?
 {
-    u32 val = cpu->GetReg(15) & ~2;
+    u32 val = cpu->R[15] & ~2;
     val += ((cpu->CurInstr & 0xFF) << 2);
     cpu->R[(cpu->CurInstr >> 8) & 0x7] = val;
     cpu->AddCycles_C();
 }
 
-void T_ADD_SPREL(ARM* cpu) // verify interlock
+void T_ADD_SPREL(ARM* cpu) // checkme: sp shouldn't be able to interlock in thumb?
 {
-    u32 val = cpu->GetReg(13);
+    u32 val = cpu->R[13];
     val += ((cpu->CurInstr & 0xFF) << 2);
     cpu->R[(cpu->CurInstr >> 8) & 0x7] = val;
     cpu->AddCycles_C();
 }
 
-void T_ADD_SP(ARM* cpu) // verify interlock
+void T_ADD_SP(ARM* cpu) // checkme: sp shouldn't be able to interlock in thumb?
 {
-    u32 val = cpu->GetReg(13);
+    u32 val = cpu->R[13];
     if (cpu->CurInstr & (1<<7))
         val -= ((cpu->CurInstr & 0x7F) << 2);
     else
diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index 52a80983..3fac1963 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -738,13 +738,13 @@ void A_STM(ARM* cpu)
 
 
 
-void T_LDR_PCREL(ARM* cpu) // verify interlock
+void T_LDR_PCREL(ARM* cpu) // checkme: can pc be interlocked?
 {
-    u32 addr = (cpu->GetReg(15) & ~0x2) + ((cpu->CurInstr & 0xFF) << 2);
+    u32 addr = (cpu->R[15] & ~0x2) + ((cpu->CurInstr & 0xFF) << 2);
     cpu->DataRead32(addr, &cpu->R[(cpu->CurInstr >> 8) & 0x7]);
 
     cpu->AddCycles_CDI();
-    cpu->SetCycles_L((cpu->CurInstr >> 8) & 0x7, 1, cpu->ILT_Norm); // checkme? ROR?
+    cpu->SetCycles_L((cpu->CurInstr >> 8) & 0x7, 1, cpu->ILT_Norm); // checkme: verify cycle count
 }
 
 
@@ -824,7 +824,7 @@ void T_LDRSH_REG(ARM* cpu)
 }
 
 
-void T_STR_IMM(ARM* cpu) // verify interlock
+void T_STR_IMM(ARM* cpu)
 {
     u32 offset = (cpu->CurInstr >> 4) & 0x7C;
     offset += cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
@@ -833,7 +833,7 @@ void T_STR_IMM(ARM* cpu) // verify interlock
     cpu->AddCycles_CD();
 }
 
-void T_LDR_IMM(ARM* cpu) // verify interlock
+void T_LDR_IMM(ARM* cpu)
 {
     u32 offset = (cpu->CurInstr >> 4) & 0x7C;
     offset += cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
@@ -845,7 +845,7 @@ void T_LDR_IMM(ARM* cpu) // verify interlock
     cpu->SetCycles_L(cpu->CurInstr & 0x7, (offset & 3) ? 2 : 1, cpu->ILT_Norm);
 }
 
-void T_STRB_IMM(ARM* cpu) // verify interlock
+void T_STRB_IMM(ARM* cpu)
 {
     u32 offset = (cpu->CurInstr >> 6) & 0x1F;
     offset += cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
@@ -854,7 +854,7 @@ void T_STRB_IMM(ARM* cpu) // verify interlock
     cpu->AddCycles_CD();
 }
 
-void T_LDRB_IMM(ARM* cpu) // verify interlock
+void T_LDRB_IMM(ARM* cpu)
 {
     u32 offset = (cpu->CurInstr >> 6) & 0x1F;
     offset += cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
@@ -865,7 +865,7 @@ void T_LDRB_IMM(ARM* cpu) // verify interlock
 }
 
 
-void T_STRH_IMM(ARM* cpu) // verify interlock
+void T_STRH_IMM(ARM* cpu)
 {
     u32 offset = (cpu->CurInstr >> 5) & 0x3E;
     offset += cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
@@ -874,7 +874,7 @@ void T_STRH_IMM(ARM* cpu) // verify interlock
     cpu->AddCycles_CD();
 }
 
-void T_LDRH_IMM(ARM* cpu) // verify interlock
+void T_LDRH_IMM(ARM* cpu)
 {
     u32 offset = (cpu->CurInstr >> 5) & 0x3E;
     offset += cpu->GetReg((cpu->CurInstr >> 3) & 0x7);
@@ -885,23 +885,23 @@ void T_LDRH_IMM(ARM* cpu) // verify interlock
 }
 
 
-void T_STR_SPREL(ARM* cpu) // verify interlock
+void T_STR_SPREL(ARM* cpu) // checkme: can sp be interlocked in thumb mode?
 {
     u32 offset = (cpu->CurInstr << 2) & 0x3FC;
-    offset += cpu->GetReg(13);
+    offset += cpu->R[13];
 
     cpu->DataWrite32(offset, cpu->GetReg((cpu->CurInstr >> 8) & 0x7, 1));
     cpu->AddCycles_CD();
 }
 
-void T_LDR_SPREL(ARM* cpu) // verify interlock
+void T_LDR_SPREL(ARM* cpu) // checkme: can sp be interlocked in thumb mode?
 {
     u32 offset = (cpu->CurInstr << 2) & 0x3FC;
-    offset += cpu->GetReg(13);
+    offset += cpu->R[13];
 
     cpu->DataRead32(offset, &cpu->R[(cpu->CurInstr >> 8) & 0x7]);
     cpu->AddCycles_CDI();
-    cpu->SetCycles_L((cpu->CurInstr >> 8) & 0x7, 1, cpu->ILT_Norm); // checkme? ROR?
+    cpu->SetCycles_L((cpu->CurInstr >> 8) & 0x7, 1, cpu->ILT_Norm); // checkme: verify cycle count
 }
 
 
@@ -952,9 +952,9 @@ void T_PUSH(ARM* cpu)
     cpu->AddCycles_CD();
 }
 
-void T_POP(ARM* cpu) // verify interlock
+void T_POP(ARM* cpu) // checkme: can sp be interlocked in thumb mode?
 {
-    u32 base = cpu->GetReg(13);
+    u32 base = cpu->R[13];
     bool first = true;
     u32 lastreg = 0;