implement msr and mrs for the x64 JIT
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1c98cefcee
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c2dd6a186d
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@ -824,7 +824,7 @@ void InvalidateITCM(u32 addr)
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void InvalidateAll()
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{
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JIT_DEBUGPRINT("invalidating all %x\n", JitBlocks.Length);
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JIT_DEBUGPRINT("invalidating all %x\n", JitBlocks.size());
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for (auto it : JitBlocks)
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{
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JitBlock* block = it.second;
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@ -38,6 +38,131 @@ const int RegisterCache<Compiler, X64Reg>::NativeRegsAvailable =
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#endif
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;
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void Compiler::A_Comp_MRS()
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{
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Comp_AddCycles_C();
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OpArg rd = MapReg(CurInstr.A_Reg(12));
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if (CurInstr.Instr & (1 << 22))
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{
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MOV(32, R(RSCRATCH), R(RCPSR));
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AND(32, R(RSCRATCH), Imm8(0x1F));
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XOR(32, R(ABI_PARAM3), R(ABI_PARAM3));
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MOV(32, R(ABI_PARAM2), Imm32(15 - 8));
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CALL(ReadBanked);
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MOV(32, rd, R(ABI_PARAM3));
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}
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else
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MOV(32, rd, R(RCPSR));
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}
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void Compiler::A_Comp_MSR()
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{
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Comp_AddCycles_C();
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OpArg val = CurInstr.Instr & (1 << 25)
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? Imm32(ROR((CurInstr.Instr & 0xFF), ((CurInstr.Instr >> 7) & 0x1E)))
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: MapReg(CurInstr.A_Reg(0));
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u32 mask = 0;
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if (CurInstr.Instr & (1<<16)) mask |= 0x000000FF;
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if (CurInstr.Instr & (1<<17)) mask |= 0x0000FF00;
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if (CurInstr.Instr & (1<<18)) mask |= 0x00FF0000;
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if (CurInstr.Instr & (1<<19)) mask |= 0xFF000000;
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if (CurInstr.Instr & (1 << 22))
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{
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MOV(32, R(RSCRATCH), R(RCPSR));
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AND(32, R(RSCRATCH), Imm8(0x1F));
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XOR(32, R(ABI_PARAM3), R(ABI_PARAM3));
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MOV(32, R(ABI_PARAM2), Imm32(15 - 8));
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CALL(ReadBanked);
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MOV(32, R(RSCRATCH2), Imm32(0xFFFFFF00));
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MOV(32, R(RSCRATCH3), Imm32(0xFFFFFFFF));
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MOV(32, R(RSCRATCH), R(RCPSR));
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AND(32, R(RSCRATCH), Imm8(0x1F));
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CMP(32, R(RSCRATCH), Imm8(0x10));
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CMOVcc(32, RSCRATCH2, R(RSCRATCH3), CC_NE);
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AND(32, R(RSCRATCH2), Imm32(mask));
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MOV(32, R(RSCRATCH), R(RSCRATCH2));
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NOT(32, R(RSCRATCH));
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AND(32, R(ABI_PARAM3), R(RSCRATCH));
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AND(32, R(RSCRATCH2), val);
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OR(32, R(ABI_PARAM3), R(RSCRATCH2));
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MOV(32, R(RSCRATCH), R(RCPSR));
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AND(32, R(RSCRATCH), Imm8(0x1F));
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MOV(32, R(ABI_PARAM2), Imm32(15 - 8));
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CALL(WriteBanked);
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}
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else
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{
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mask &= 0xFFFFFFDF;
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CPSRDirty = true;
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if ((mask & 0xFF) == 0)
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{
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AND(32, R(RCPSR), Imm32(~mask));
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if (val.IsImm())
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{
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MOV(32, R(RSCRATCH), val);
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AND(32, R(RSCRATCH), Imm32(mask));
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OR(32, R(RCPSR), R(RSCRATCH));
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}
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else
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{
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OR(32, R(RCPSR), Imm32(val.Imm32() & mask));
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}
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}
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else
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{
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MOV(32, R(RSCRATCH2), Imm32(mask));
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MOV(32, R(RSCRATCH3), R(RSCRATCH2));
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AND(32, R(RSCRATCH3), Imm32(0xFFFFFF00));
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MOV(32, R(RSCRATCH), R(RCPSR));
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AND(32, R(RSCRATCH), Imm8(0x1F));
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CMP(32, R(RSCRATCH), Imm8(0x10));
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CMOVcc(32, RSCRATCH2, R(RSCRATCH3), CC_E);
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MOV(32, R(RSCRATCH3), R(RCPSR));
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// I need you ANDN
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MOV(32, R(RSCRATCH), R(RSCRATCH2));
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NOT(32, R(RSCRATCH));
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AND(32, R(RCPSR), R(RSCRATCH));
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AND(32, R(RSCRATCH2), val);
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OR(32, R(RCPSR), R(RSCRATCH2));
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BitSet16 hiRegsLoaded(RegCache.LoadedRegs & 0x7F00);
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if (Thumb || CurInstr.Cond() >= 0xE)
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RegCache.Flush();
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else
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{
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// the ugly way...
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// we only save them, to load and save them again
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for (int reg : hiRegsLoaded)
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SaveReg(reg, RegCache.Mapping[reg]);
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}
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MOV(32, R(ABI_PARAM3), R(RCPSR));
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MOV(32, R(ABI_PARAM2), R(RSCRATCH3));
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MOV(64, R(ABI_PARAM1), R(RCPU));
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CALL((void*)&ARM::UpdateMode);
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if (!Thumb && CurInstr.Cond() < 0xE)
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{
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for (int reg : hiRegsLoaded)
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LoadReg(reg, RegCache.Mapping[reg]);
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}
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}
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}
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}
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/*
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We'll repurpose this .bss memory
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@ -328,7 +453,7 @@ const Compiler::CompileFunc A_Comp[ARMInstrInfo::ak_Count] =
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// Branch
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F(A_Comp_BranchImm), F(A_Comp_BranchImm), F(A_Comp_BranchImm), F(A_Comp_BranchXchangeReg), F(A_Comp_BranchXchangeReg),
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// system stuff
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NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, F(A_Comp_MSR), F(A_Comp_MSR), F(A_Comp_MRS), NULL, NULL, NULL,
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F(Nop)
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};
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@ -100,6 +100,9 @@ public:
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void A_Comp_BranchImm();
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void A_Comp_BranchXchangeReg();
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void A_Comp_MRS();
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void A_Comp_MSR();
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void T_Comp_ShiftImm();
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void T_Comp_AddSub_();
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void T_Comp_ALU_Imm8();
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@ -427,6 +427,10 @@ Info Decode(bool thumb, u32 num, u32 instr)
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res.Kind = ak_UNK;
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}
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}
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if (res.Kind == ak_MRS && !(instr & (1 << 22)))
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res.ReadFlags |= flag_N | flag_Z | flag_C | flag_V;
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if ((res.Kind == ak_MSR_IMM || res.Kind == ak_MSR_REG) && instr & (1 << 19))
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res.WriteFlags |= flag_N | flag_Z | flag_C | flag_V;
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if (data & A_Read0)
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res.SrcRegs |= 1 << (instr & 0xF);
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