From c0075404fd32429820cce7f7c0e73b4936a2e13d Mon Sep 17 00:00:00 2001
From: DesperateProgrammer <tim.seidel@rwth-aachen.de>
Date: Thu, 1 Feb 2024 13:25:07 +0100
Subject: [PATCH] Included the I/DCache Streaming disable bits in cache lookup

---
 src/CP15.cpp         | 32 ++++++++++++++++++++++++++++++++
 src/CP15_Constants.h |  2 ++
 2 files changed, 34 insertions(+)

diff --git a/src/CP15.cpp b/src/CP15.cpp
index f6f11a7a..5861f15f 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -381,6 +381,20 @@ u32 ARMv5::ICacheLookup(const u32 addr)
         {
             CodeCycles = 1;
             u32 *cacheLine = (u32 *)&ICache[(id+set) << ICACHE_LINELENGTH_LOG2];
+            if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_ICACHE_STREAMING)
+            {
+                // Disabled ICACHE Streaming:
+                // retreive the data from memory, even if the data was cached
+                // See arm946e-s Rev 1 technical manual, 2.3.15 "Register 15, test State Register")
+                CodeCycles = NDS.ARM9MemTimings[tag >> 14][2]; 
+                if (CodeMem.Mem)
+                {
+                    return *(u32*)&CodeMem.Mem[(addr & CodeMem.Mask) & ~3];
+                } else
+                {
+                    return NDS.ARM9Read32(addr & ~3);
+                }     
+            }
             return cacheLine[(addr & (ICACHE_LINELENGTH -1)) >> 2];
         }
     }
@@ -519,6 +533,24 @@ u32 ARMv5::DCacheLookup(const u32 addr)
         {
             DataCycles = 1;
             u32 *cacheLine = (u32 *)&DCache[(id+set) << DCACHE_LINELENGTH_LOG2];
+            if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_DCACHE_STREAMING)
+            {
+                // Disabled DCACHE Streaming:
+                // retreive the data from memory, even if the data was cached
+                // See arm946e-s Rev 1 technical manual, 2.3.15 "Register 15, test State Register")
+                DataCycles = NDS.ARM9MemTimings[tag >> 14][2]; 
+                if (addr < ITCMSize)
+                {
+                    return *(u32*)&ITCM[addr & (ITCMPhysicalSize - 3)];
+                } else
+                if ((addr & DTCMMask) == DTCMBase)
+                {
+                    return *(u32*)&DTCM[addr & (DTCMPhysicalSize - 3)];
+                } else
+                {
+                    return BusRead32(addr & ~3);
+                }     
+            }
             return cacheLine[(addr & (ICACHE_LINELENGTH -1)) >> 2];
         }
     }
diff --git a/src/CP15_Constants.h b/src/CP15_Constants.h
index 0d786afa..b148372d 100644
--- a/src/CP15_Constants.h
+++ b/src/CP15_Constants.h
@@ -92,6 +92,8 @@ constexpr u32 CP15_CACHE_CR_DCACHEENABLE = (1 << 2);
 constexpr u32 CP15_CACHE_CR_WRITEBUFFERENABLE = (1 << 3);
 
 /* CP15 BIST Test State register */
+constexpr u32 CP15_BIST_TR_DISABLE_ICACHE_STREAMING = (1 << 11);
+constexpr u32 CP15_BIST_TR_DISABLE_DCACHE_STREAMING = (1 << 12);
 constexpr u32 CP15_BIST_TR_DISABLE_ICACHE_LINEFILL = (1 << 9);
 constexpr u32 CP15_BIST_TR_DISABLE_DCACHE_LINEFILL = (1 << 10);