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Formatting corrections 

Removed premature optimization and replaced them with [[(un)likely]]
This commit is contained in:
DesperateProgrammer 2024-02-07 08:10:27 +01:00
parent 01bb5f1fe2
commit b2d196cd64
1 changed files with 50 additions and 89 deletions
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81
src/CP15.cpp
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@ -377,7 +377,7 @@ u32 ARMv5::ICacheLookup(const u32 addr)
{
CodeCycles = 1;
u32 *cacheLine = (u32 *)&ICache[(id+set) << ICACHE_LINELENGTH_LOG2];
if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_ICACHE_STREAMING)
if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_ICACHE_STREAMING) [[unlikely]]
{
// Disabled ICACHE Streaming:
// retreive the data from memory, even if the data was cached
@ -399,7 +399,7 @@ u32 ARMv5::ICacheLookup(const u32 addr)
// We do not fill the cacheline if it is disabled in the
// BIST test State register (See arm946e-s Rev 1 technical manual, 2.3.15 "Register 15, test State Register")
if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_ICACHE_LINEFILL)
if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_ICACHE_LINEFILL) [[unlikely]]
{
CodeCycles = NDS.ARM9MemTimings[tag >> 14][2];
if (CodeMem.Mem)
@ -412,17 +412,8 @@ u32 ARMv5::ICacheLookup(const u32 addr)
}
u32 line;
#if 0
// caclulate in which cacheline the data is to be filled
// The code below is doing the same as the if-less below
// It increases performance by reducing banches.
// The code is kept here for readability.
//
// NOTE: If you need to update either part, you need
// to update the other too to keep them in sync!
//
if (CP15Control & CP15_CACHE_CR_ROUNDROBIN)
if (CP15Control & CP15_CACHE_CR_ROUNDROBIN) [[likely]]
{
line = ICacheCount;
ICacheCount = (line+1) & (ICACHE_SETS-1);
@ -434,7 +425,7 @@ u32 ARMv5::ICacheLookup(const u32 addr)
if (ICacheLockDown)
{
if (ICacheLockDown & CACHE_LOCKUP_L)
if (ICacheLockDown & CACHE_LOCKUP_L) [[unlikely]]
{
// load into locked up cache
// into the selected set
@ -446,17 +437,7 @@ u32 ARMv5::ICacheLookup(const u32 addr)
}
}
#else
// Do the same as above but instead of using if-else
// utilize the && and || operators to skip parts of the operations
// With the order of comparison we can put the most likely path
// checked first
bool doLockDown = (ICacheLockDown & CACHE_LOCKUP_L);
bool roundRobin = CP15Control & CP15_CACHE_CR_ROUNDROBIN;
(!roundRobin && (line = RandomLineIndex())) || (roundRobin && (ICacheCount = line = ((ICacheCount+1) & (ICACHE_SETS-1)))) ;
(!doLockDown && (line = (line | ICacheLockDown & (ICACHE_SETS-1))+id)) || (doLockDown && (line = (ICacheLockDown & (ICACHE_SETS-1))+id));
#endif
line += id;
u32* ptr = (u32 *)&ICache[line << ICACHE_LINELENGTH_LOG2];
@ -488,7 +469,7 @@ void ARMv5::ICacheInvalidateByAddr(const u32 addr)
{
if ((ICacheTags[id+set] & ~(CACHE_FLAG_DIRTY_MASK | CACHE_FLAG_SET_MASK)) == tag)
{
ICacheTags[id+set] &= ~CACHE_FLAG_VALID; ;
ICacheTags[id+set] &= ~CACHE_FLAG_VALID;
return;
}
}
@ -502,7 +483,7 @@ void ARMv5::ICacheInvalidateBySetAndWay(const u8 cacheSet, const u8 cacheLine)
return;
u32 idx = (cacheLine << ICACHE_SETS_LOG2) + cacheSet;
ICacheTags[idx] &= ~CACHE_FLAG_VALID; ;
ICacheTags[idx] &= ~CACHE_FLAG_VALID;
}
@ -510,7 +491,7 @@ void ARMv5::ICacheInvalidateAll()
{
#pragma GCC ivdep
for (int i = 0; i < ICACHE_SIZE / ICACHE_LINELENGTH; i++)
ICacheTags[i] &= ~CACHE_FLAG_VALID; ;
ICacheTags[i] &= ~CACHE_FLAG_VALID;
}
bool ARMv5::IsAddressICachable(const u32 addr) const
@ -530,7 +511,7 @@ u32 ARMv5::DCacheLookup(const u32 addr)
{
DataCycles = 1;
u32 *cacheLine = (u32 *)&DCache[(id+set) << DCACHE_LINELENGTH_LOG2];
if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_DCACHE_STREAMING)
if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_DCACHE_STREAMING) [[unlikely]]
{
// Disabled DCACHE Streaming:
// retreive the data from memory, even if the data was cached
@ -557,7 +538,7 @@ u32 ARMv5::DCacheLookup(const u32 addr)
// We do not fill the cacheline if it is disabled in the
// BIST test State register (See arm946e-s Rev 1 technical manual, 2.3.15 "Register 15, test State Register")
if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_DCACHE_LINEFILL)
if (CP15BISTTestStateRegister & CP15_BIST_TR_DISABLE_DCACHE_LINEFILL) [[unlikely]]
{
DataCycles = NDS.ARM9MemTimings[tag >> 14][2];
if (addr < ITCMSize)
@ -574,51 +555,31 @@ u32 ARMv5::DCacheLookup(const u32 addr)
}
u32 line;
#if 0
// caclulate in which cacheline the data is to be filled
// The code below is doing the same as the if-less below
// It increases performance by reducing banches.
// The code is kept here for readability.
//
// NOTE: If you need to update either part, you need
// to update the other too to keep them in sync!
//
if (CP15Control & CP15_CACHE_CR_ROUNDROBIN)
if (CP15Control & CP15_CACHE_CR_ROUNDROBIN) [[likely]]
{
line = DCacheCount;
DCacheCount = (line+1) & (DCACHE_SETS-1);
}
else
{
line = DCacheRandom();
line = RandomLineIndex();
}
// Update the selected set depending on the DCache LockDown register
if (DCacheLockDown)
{
if (DCacheLockDown & CACHE_LOCKUP_L)
if (DCacheLockDown & CACHE_LOCKUP_L) [[unlikely]]
{
// load into locked up cache
// into the selected set
line = (DCacheLockDown & (DCACHE_SETS-1)) + id;
line = DCacheLockDown & (DCACHE_SETS-1);
} else
{
u8 minSet = ICacheLockDown & (DCACHE_SETS-1);
line = (line | minSet) + id;
u8 minSet = DCacheLockDown & (DCACHE_SETS-1);
line = line | minSet;
}
}
#else
// Do the same as above but instead of using if-else
// utilize the && and || operators to skip parts of the operations
// With the order of comparison we can put the most likely path
// checked first
bool doLockDown = (DCacheLockDown & CACHE_LOCKUP_L);
bool roundRobin = CP15Control & CP15_CACHE_CR_ROUNDROBIN;
(!roundRobin && (line = RandomLineIndex())) || (roundRobin && (DCacheCount = line = ((DCacheCount+1) & (DCACHE_SETS-1))));
(!doLockDown && (line = (line | DCacheLockDown & (DCACHE_SETS-1))+id)) || (doLockDown && (line = (DCacheLockDown & (DCACHE_SETS-1))+id));
#endif
line += id;
u32* ptr = (u32 *)&DCache[line << DCACHE_LINELENGTH_LOG2];
@ -726,7 +687,7 @@ bool ARMv5::DCacheWrite16(const u32 addr, const u16 val)
bool ARMv5::DCacheWrite8(const u32 addr, const u8 val)
{
const u32 tag = (addr & ~(DCACHE_LINELENGTH - 1)) | CACHE_FLAG_VALID;
const u32 id = ((addr >> DCACHE_LINELENGTH_LOG2) & (DCACHE_LINESPERSET-1)) << DCACHE_SETS_LOG2;;
const u32 id = ((addr >> DCACHE_LINELENGTH_LOG2) & (DCACHE_LINESPERSET-1)) << DCACHE_SETS_LOG2;
//Log(LogLevel::Debug, "Cache write 8: %08lx <= %02x\n", addr, val);
@ -769,7 +730,7 @@ void ARMv5::DCacheInvalidateByAddr(const u32 addr)
if ((DCacheTags[id+set] & ~(CACHE_FLAG_DIRTY_MASK | CACHE_FLAG_SET_MASK)) == tag)
{
//Log(LogLevel::Debug,"DCache invalidated %08lx\n", addr & ~(ICACHE_LINELENGTH-1));
DCacheTags[id+set] &= ~CACHE_FLAG_VALID; ;
DCacheTags[id+set] &= ~CACHE_FLAG_VALID;
return;
}
}
@ -783,7 +744,7 @@ void ARMv5::DCacheInvalidateBySetAndWay(const u8 cacheSet, const u8 cacheLine)
return;
u32 idx = (cacheLine << DCACHE_SETS_LOG2) + cacheSet;
DCacheTags[idx] &= ~CACHE_FLAG_VALID; ;
DCacheTags[idx] &= ~CACHE_FLAG_VALID;
}
@ -791,7 +752,7 @@ void ARMv5::DCacheInvalidateAll()
{
#pragma GCC ivdep
for (int i = 0; i < DCACHE_SIZE / DCACHE_LINELENGTH; i++)
DCacheTags[i] &= ~CACHE_FLAG_VALID; ;
DCacheTags[i] &= ~CACHE_FLAG_VALID;
}
void ARMv5::DCacheClearAll()