From 8fff17f03f2d13be9f74af9607c048ab738fe3ac Mon Sep 17 00:00:00 2001
From: Jaklyy <102590697+Jaklyy@users.noreply.github.com>
Date: Sat, 19 Oct 2024 11:01:16 -0400
Subject: [PATCH 1/2] fix resets

---
 src/ARM.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/ARM.cpp b/src/ARM.cpp
index 8bcdd452..a67ef56e 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -202,6 +202,7 @@ void ARMv5::Reset()
     PU_Map = PU_PrivMap;
     Store = false;
     
+    ITCMTimestamp = 0;
     TimestampActual = 0;
     ILCurrReg = 16;
     ILPrevReg = 16;

From e254ac3240a503213ca784779dfe32333a6ea803 Mon Sep 17 00:00:00 2001
From: Jaklyy <102590697+Jaklyy@users.noreply.github.com>
Date: Sat, 19 Oct 2024 12:35:27 -0400
Subject: [PATCH 2/2] fix ldrd/strd itcm timings

---
 src/ARMInterpreter_LoadStore.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index 28256207..adbd1121 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -317,6 +317,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     ExecuteStage<true>(cpu, ilmask | (1 << ((cpu->CurInstr>>16) & 0xF))); \
     bool dabort = !cpu->DataRead32(offset, &cpu->R[r]); \
     u32 val; dabort |= !cpu->DataRead32S(offset+4, &val); \
+    if (cpu->DataRegion == Mem9_ITCM) cpu->NDS.ARM9Timestamp += 2; \
     cpu->AddCycles_CDI(); \
     if (dabort) { \
         ((ARMv5*)cpu)->DataAbort(); \
@@ -337,6 +338,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     ExecuteStage<true>(cpu, ilmask | (1 << ((cpu->CurInstr>>16) & 0xF))); \
     bool dabort = !cpu->DataRead32(addr, &cpu->R[r]); \
     u32 val; dabort |= !cpu->DataRead32S(addr+4, &val); \
+    if (cpu->DataRegion == Mem9_ITCM) cpu->NDS.ARM9Timestamp += 2; \
     cpu->AddCycles_CDI(); \
     if (dabort) { \
         ((ARMv5*)cpu)->DataAbort(); \
@@ -359,6 +361,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     bool dabort = !cpu->DataWrite32(offset, cpu->R[r]); /* yes, this data abort behavior is on purpose */ \
     u32 storeval = cpu->R[r+1]; if (r == 14) storeval+=4; \
     dabort |= !cpu->DataWrite32S (offset+4, storeval); /* no, i dont understand it either */ \
+    if (cpu->DataRegion == Mem9_ITCM) cpu->NDS.ARM9Timestamp += 2; \
     cpu->AddCycles_CD(); \
     if (dabort) [[unlikely]] { \
         ((ARMv5*)cpu)->DataAbort(); \
@@ -375,6 +378,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     bool dabort = !cpu->DataWrite32(addr, cpu->R[r]); \
     u32 storeval = cpu->R[r+1]; if (r == 14) storeval+=4; \
     dabort |= !cpu->DataWrite32S (addr+4, storeval); \
+    if (cpu->DataRegion == Mem9_ITCM) cpu->NDS.ARM9Timestamp += 2; \
     cpu->AddCycles_CD(); \
     if (dabort) [[unlikely]] { \
         ((ARMv5*)cpu)->DataAbort(); \