From a2f711c04852558bdd025de3367655ff5db4d045 Mon Sep 17 00:00:00 2001
From: DesperateProgrammer <tim.seidel@rwth-aachen.de>
Date: Thu, 18 Jan 2024 09:39:33 +0100
Subject: [PATCH] Added CP15 Data and Instruction Cache Lockdown Register

---
 src/ARM.h    |  1 +
 src/CP15.cpp | 23 +++++++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/src/ARM.h b/src/ARM.h
index 1e0b71b8..c6711333 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -322,6 +322,7 @@ public:
     u32 RNGSeed;
 
     u32 DTCMSetting, ITCMSetting;
+    u32 DCacheLockDown, ICacheLockDown;
 
     // for aarch64 JIT they need to go up here
     // to be addressable by a 12-bit immediate
diff --git a/src/CP15.cpp b/src/CP15.cpp
index 58137fdd..ebebf975 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -55,6 +55,9 @@ void ARMv5::CP15Reset()
     DTCMBase = 0xFFFFFFFF;
     DTCMMask = 0;
 
+    ICacheLockDown = 0;
+    DCacheLockDown = 0;
+
     memset(ICache, 0, 0x2000);
     ICacheInvalidateAll();
     memset(ICacheCount, 0, 64);
@@ -628,6 +631,22 @@ void ARMv5::CP15Write(u32 id, u32 val)
         //printf("flush data cache SI\n");
         return;
 
+    case 0x900:
+        // Cache Lockdown - Format B
+        //    Bit 31: Lock bit
+        //    Bit 0..Way-1: locked ways
+        //      The Cache is 4 way associative
+        // But all bits are r/w
+        DCacheLockDown = val ;
+        return;
+    case 0x901:
+        // Cache Lockdown - Format B
+        //    Bit 31: Lock bit
+        //    Bit 0..Way-1: locked ways
+        //      The Cache is 4 way associative
+        // But all bits are r/w
+        ICacheLockDown = val;
+        return;
 
     case 0x910:
         DTCMSetting = val & 0xFFFFF03E;
@@ -751,6 +770,10 @@ u32 ARMv5::CP15Read(u32 id) const
     case 0x671:
         return PU_Region[(id >> 4) & 0xF];
 
+    case 0x900:
+        return DCacheLockDown;
+    case 0x901:
+        return ICacheLockDown;
 
     case 0x910:
         return DTCMSetting;