diff --git a/src/CP15.cpp b/src/CP15.cpp
index 58105aa0..2a3936d9 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -1181,7 +1181,7 @@ u32 ARMv5::CP15Read(u32 id) const
         return 0x41059461;
 
     case 0x001: // cache type
-        return CACHE_TR_LOCKUP_TYPE_B | CACHE_TR_NONUNIFIED
+        return CACHE_TR_LOCKDOWN_TYPE_B | CACHE_TR_NONUNIFIED
                | (DCACHE_LINELENGTH_ENCODED << 12) | (DCACHE_SETS_LOG2 << 15) | ((DCACHE_SIZE_LOG2 - 9) << 18)
                | (ICACHE_LINELENGTH_ENCODED << 0) | (ICACHE_SETS_LOG2 << 3) | ((ICACHE_SIZE_LOG2 - 9) << 6);
 
diff --git a/src/MemConstants.h b/src/MemConstants.h
index af6f89f7..332b9b18 100644
--- a/src/MemConstants.h
+++ b/src/MemConstants.h
@@ -57,6 +57,9 @@ constexpr u32 CACHE_FLAG_VALID = (1 << 4);
 constexpr u32 CACHE_FLAG_DIRTY_LOWERHALF = (1 << 2);
 constexpr u32 CACHE_FLAG_DIRTY_UPPERHALF = (1 << 3);
 
+constexpr u32 CACHE_TR_LOCKDOWN_TYPE_B = (7 << 25);
+constexpr u32 CACHE_TR_NONUNIFIED = (1 << 24);
+
 constexpr u32 CACHE_LOCKUP_L = (1 << 31);
 
 constexpr u32 CP15_CR_MPUENABLE = (1 << 0);