add a few missing 32bit I/O accesses (IPC, SPI)
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parent
65be1840f0
commit
9fdc1de6fe
11
src/NDS.cpp
11
src/NDS.cpp
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@ -3001,6 +3001,7 @@ u32 ARM9IORead32(u32 addr)
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case 0x04000130: return (KeyInput & 0xFFFF) | (KeyCnt << 16);
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case 0x04000180: return IPCSync9;
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case 0x04000184: return ARM9IORead16(addr);
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case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
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case 0x040001A4: return NDSCart::ROMCnt;
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@ -3378,10 +3379,11 @@ void ARM9IOWrite32(u32 addr, u32 val)
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case 0x04000130:
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KeyCnt = val >> 16;
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return;
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case 0x04000180:
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case 0x04000184:
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ARM9IOWrite16(addr, val);
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return;
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case 0x04000188:
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if (IPCFIFOCnt9 & 0x8000)
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{
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@ -3640,6 +3642,7 @@ u32 ARM7IORead32(u32 addr)
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case 0x04000138: return RTC::Read();
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case 0x04000180: return IPCSync7;
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case 0x04000184: return ARM7IORead16(addr);
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case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
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case 0x040001A4: return NDSCart::ROMCnt;
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@ -3940,6 +3943,7 @@ void ARM7IOWrite32(u32 addr, u32 val)
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case 0x04000138: RTC::Write(val & 0xFFFF, false); return;
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case 0x04000180:
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case 0x04000184:
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ARM7IOWrite16(addr, val);
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return;
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case 0x04000188:
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@ -3984,6 +3988,11 @@ void ARM7IOWrite32(u32 addr, u32 val)
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case 0x040001B0: *(u32*)&ROMSeed0[8] = val; return;
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case 0x040001B4: *(u32*)&ROMSeed1[8] = val; return;
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case 0x040001C0:
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SPI::WriteCnt(val & 0xFFFF);
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SPI::WriteData((val >> 16) & 0xFF);
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return;
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case 0x04000208: IME[1] = val & 0x1; UpdateIRQ(1); return;
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case 0x04000210: IE[1] = val; UpdateIRQ(1); return;
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case 0x04000214: IF[1] &= ~val; UpdateIRQ(1); return;
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