wifi: fix TX start logic (it is possible to write TXREQ then TXLOC)
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parent
fb1eb43fb4
commit
9e36cba941
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@ -228,6 +228,9 @@ void SetupDirectBoot()
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PowerControl9 = 0x820F;
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GPU::DisplaySwap(PowerControl9);
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// checkme
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RCnt = 0x8000;
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SPU::SetBias(0x200);
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ARM7BIOSProt = 0x1204;
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38
src/Wifi.cpp
38
src/Wifi.cpp
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@ -288,41 +288,40 @@ void StartTX_Beacon()
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IOPORT(W_TXBusy) |= 0x0010;
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}
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// TODO eventually: there is a small delay to firing TX
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void FireTX()
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{
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u16 txbusy = IOPORT(W_TXBusy);
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printf("attempting to fire TX: %04X %04X\n", txbusy, IOPORT(W_TXSlotLoc2));
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u16 txreq = IOPORT(W_TXReqRead);
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if ((txreq & 0x0001) && (IOPORT(W_TXSlotLoc1) & 0x8000)) txbusy |= 0x0001;
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if ((txreq & 0x0002) && (IOPORT(W_TXSlotCmd) & 0x8000)) txbusy |= 0x0002;
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if ((txreq & 0x0004) && (IOPORT(W_TXSlotLoc2) & 0x8000)) txbusy |= 0x0004;
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if ((txreq & 0x0008) && (IOPORT(W_TXSlotLoc3) & 0x8000)) txbusy |= 0x0008;
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IOPORT(W_TXBusy) = txbusy;
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if (txbusy & 0x0008)
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{
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if (IOPORT(W_TXSlotLoc3) & 0x8000)
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{
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StartTX_LocN(3, 2);
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return;
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}
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}
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if (txbusy & 0x0004)
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{
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if (IOPORT(W_TXSlotLoc2) & 0x8000)
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{
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StartTX_LocN(2, 1);
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return;
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}
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}
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// TODO: CMD
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if (txbusy & 0x0001)
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{
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if (IOPORT(W_TXSlotLoc1) & 0x8000)
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{
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StartTX_LocN(0, 0);
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return;
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}
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}
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IOPORT(W_TXBusy) = 0;
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}
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void ProcessTX(TXSlot* slot, int num)
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{
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slot->CurPhaseTime--;
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@ -887,7 +886,6 @@ void Write(u32 addr, u16 val)
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return;
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case W_TXReqSet:
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IOPORT(W_TXReqRead) |= val;
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IOPORT(W_TXBusy) |= (val & 0x000F);
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FireTX();
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// CHECKME!!!!!!!!!!!
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return;
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@ -936,10 +934,16 @@ void Write(u32 addr, u16 val)
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val &= 0x0FFF;
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break;
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case 0x090:
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case 0x0A0:
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case 0x0A4:
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case 0x0A8:
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case W_TXSlotCmd:
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case W_TXSlotLoc1:
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case W_TXSlotLoc2:
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case W_TXSlotLoc3:
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// checkme: is it possible to cancel a queued transfer that hasn't started yet
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// by clearing bit15 here?
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IOPORT(addr&0xFFF) = val;
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FireTX();
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return;
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case 0x094:
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printf("wifi: trying to send packet. %08X=%04X. TXREQ=%04X\n", addr, val, IOPORT(W_TXReqRead));
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break;
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