diff --git a/src/CP15.cpp b/src/CP15.cpp
index ef7f6347..fef3eac1 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -380,6 +380,24 @@ void ARMv5::ICacheLookup(u32 addr)
         line = RandomLineIndex();
     }
 
+    if (ICacheLockDown)
+    {
+        if (ICacheLockDown & CACHE_LOCKUP_L)
+        {
+            // load into locked up cache
+            // into the selected set
+            line = ICacheLockDown & (ICACHE_SETS-1);
+        } else
+        {
+            u8 minSet = ICacheLockDown & (ICACHE_SETS-1);
+            if (minSet)
+            {
+                // part of the cache is locked up and only the cachelines 
+                line = (line % (ICACHE_SETS - minSet)) + minSet;
+            }
+        }
+    }
+
     line += id;
 
     addr &= ~(ICACHE_LINELENGTH-1);
@@ -474,6 +492,24 @@ void ARMv5::DCacheLookup(u32 addr)
         line = RandomLineIndex();
     }
 
+    if (DCacheLockDown)
+    {
+        if (DCacheLockDown & CACHE_LOCKUP_L)
+        {
+            // load into locked up cache
+            // into the selected set
+            line = DCacheLockDown & (DCACHE_SETS-1);
+        } else
+        {
+            u8 minSet = DCacheLockDown & (DCACHE_SETS-1);
+            if (minSet)
+            {
+                // part of the cache is locked up and only the cachelines 
+                line = (line % (DCACHE_SETS - minSet)) + minSet;
+            }
+        }
+    }
+
     line += id;
 
     addr &= ~(DCACHE_LINELENGTH-1);
@@ -856,6 +892,10 @@ void ARMv5::CP15Write(u32 id, u32 val)
         // Test and clean (optional)
         // Is not present on the NDS/DSi
         return;   
+    case 0x7A4:
+        // Drain Write Buffer: Stall until all write back completed
+        // TODO when write back was implemented instead of write through
+        return;
 
     case 0x7D1:
         Log(LogLevel::Debug,"Prefetch instruction cache MVA\n");
diff --git a/src/MemConstants.h b/src/MemConstants.h
index 6b378f7a..af6f89f7 100644
--- a/src/MemConstants.h
+++ b/src/MemConstants.h
@@ -57,6 +57,8 @@ constexpr u32 CACHE_FLAG_VALID = (1 << 4);
 constexpr u32 CACHE_FLAG_DIRTY_LOWERHALF = (1 << 2);
 constexpr u32 CACHE_FLAG_DIRTY_UPPERHALF = (1 << 3);
 
+constexpr u32 CACHE_LOCKUP_L = (1 << 31);
+
 constexpr u32 CP15_CR_MPUENABLE = (1 << 0);
 constexpr u32 CP15_CR_BIGENDIAN = (1 << 7);
 constexpr u32 CP15_CR_HIGHEXCEPTIONBASE = (1 << 13);