remove some UB

- savestates used to read a four bytes from a single byte value
- a few unassigned variables
- some other things
- also make the ROR macro an inline function

src/ARM.h

@@ -24,7 +24,10 @@
 #include "types.h"
 #include "NDS.h"
 
-#define ROR(x, n) (((x) >> (n)) | ((x) << (32-(n))))
+inline u32 ROR(u32 x, u32 n)
+{
+    return (x >> (n&0x1F)) | (x << ((32-n)&0x1F));
+}
 
 enum
 {

src/ARMJIT.cpp

@@ -1087,7 +1087,10 @@ void ResetBlockCache()
 
     InvalidLiterals.Clear();
     for (int i = 0; i < ARMJIT_Memory::memregions_Count; i++)
+    {
+        if (FastBlockLookupRegions[i])
             memset(FastBlockLookupRegions[i], 0xFF, CodeRegionSizes[i] * sizeof(u64) / 2);
+    }
     for (auto it = RestoreCandidates.begin(); it != RestoreCandidates.end(); it++)
         delete it->second;
     RestoreCandidates.clear();

src/ARMJIT_A64/ARMJIT_ALU.cpp

@@ -436,7 +436,7 @@ void Compiler::A_Comp_GetOp2(bool S, Op2& op2)
         Comp_AddCycles_C();
 
         u32 shift = (CurInstr.Instr >> 7) & 0x1E;
-        u32 imm = ROR(CurInstr.Instr & 0xFF, shift);
+        u32 imm = ::ROR(CurInstr.Instr & 0xFF, shift);
 
         if (S && shift && (CurInstr.SetFlags & 0x2))
         {
@@ -447,7 +447,7 @@ void Compiler::A_Comp_GetOp2(bool S, Op2& op2)
                 ANDI2R(RCPSR, RCPSR, ~(1 << 29));
         }
 
-        op2 = Op2(ROR(CurInstr.Instr & 0xFF, (CurInstr.Instr >> 7) & 0x1E));    
+        op2 = Op2(imm);    
     }
     else
     {
@@ -523,7 +523,7 @@ void Compiler::A_Comp_ALUMovOp()
                 case ST_LSL: LSL(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
                 case ST_LSR: LSR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
                 case ST_ASR: ASR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
-                case ST_ROR: ROR_(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
+                case ST_ROR: ROR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
                 }
             }
             else

src/ARMJIT_A64/ARMJIT_Compiler.cpp

@@ -76,7 +76,7 @@ void Compiler::A_Comp_MSR()
     if (CurInstr.Instr & (1 << 25))
     {
         val = W0;
-        MOVI2R(val, ROR((CurInstr.Instr & 0xFF), ((CurInstr.Instr >> 7) & 0x1E)));
+        MOVI2R(val, ::ROR((CurInstr.Instr & 0xFF), ((CurInstr.Instr >> 7) & 0x1E)));
     }
     else
     {

src/ARMJIT_A64/ARMJIT_LoadStore.cpp

@@ -65,7 +65,7 @@ bool Compiler::Comp_MemLoadLiteral(int size, bool signExtend, int rd, u32 addr)
     if (size == 32)
     {
         CurCPU->DataRead32(addr & ~0x3, &val);
-        val = ROR(val, (addr & 0x3) << 3);
+        val = ::ROR(val, (addr & 0x3) << 3);
     }
     else if (size == 16)
     {
@@ -151,7 +151,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags)
     {
         if (offset.Reg.ShiftType == ST_ROR)
         {
-            ROR_(W0, offset.Reg.Rm, offset.Reg.ShiftAmount);
+            ROR(W0, offset.Reg.Rm, offset.Reg.ShiftAmount);
             offset = Op2(W0);
         }
 
@@ -220,7 +220,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, Op2 offset, int size, int flags)
                 if (size == 32)
                 {
                     if (staticAddress & 0x3)
-                        ROR_(rdMapped, W0, (staticAddress & 0x3) << 3);
+                        ROR(rdMapped, W0, (staticAddress & 0x3) << 3);
                     else
                         MOV(rdMapped, W0);
                 }

src/ARMJIT_x64/ARMJIT_ALU.cpp

@@ -110,7 +110,7 @@ OpArg Compiler::A_Comp_GetALUOp2(bool S, bool& carryUsed)
         Comp_AddCycles_C();
 
         u32 shift = (CurInstr.Instr >> 7) & 0x1E;
-        u32 imm = ROR(CurInstr.Instr & 0xFF, shift);
+        u32 imm = ::ROR(CurInstr.Instr & 0xFF, shift);
 
         carryUsed = false;
         if (S && shift)
@@ -493,7 +493,7 @@ OpArg Compiler::Comp_RegShiftReg(int op, Gen::OpArg rs, Gen::OpArg rm, bool S, b
     {
         if (S)
             BT(32, R(RSCRATCH), Imm8(31));
-        ROR_(32, R(RSCRATCH), R(ECX));
+        ROR(32, R(RSCRATCH), R(ECX));
         if (S)
             SETcc(CC_C, R(RSCRATCH2));
     }
@@ -555,7 +555,7 @@ OpArg Compiler::Comp_RegShiftImm(int op, int amount, OpArg rm, bool S, bool& car
     case 3: // ROR
         MOV(32, R(RSCRATCH), rm);
         if (amount > 0)
-            ROR_(32, R(RSCRATCH), Imm8(amount));
+            ROR(32, R(RSCRATCH), Imm8(amount));
         else
         {
             BT(32, R(RCPSR), Imm8(29));

src/ARMJIT_x64/ARMJIT_Compiler.cpp

@@ -106,7 +106,7 @@ void Compiler::A_Comp_MSR()
     Comp_AddCycles_C();
 
     OpArg val = CurInstr.Instr & (1 << 25)
-        ? Imm32(ROR((CurInstr.Instr & 0xFF), ((CurInstr.Instr >> 7) & 0x1E)))
+        ? Imm32(::ROR((CurInstr.Instr & 0xFF), ((CurInstr.Instr >> 7) & 0x1E)))
         : MapReg(CurInstr.A_Reg(0));
 
     u32 mask = 0;

src/ARMJIT_x64/ARMJIT_LoadStore.cpp

@@ -73,7 +73,7 @@ bool Compiler::Comp_MemLoadLiteral(int size, bool signExtend, int rd, u32 addr)
     if (size == 32)
     {
         CurCPU->DataRead32(addr & ~0x3, &val);
-        val = ROR(val, (addr & 0x3) << 3);
+        val = ::ROR(val, (addr & 0x3) << 3);
     }
     else if (size == 16)
     {
@@ -225,13 +225,13 @@ void Compiler::Comp_MemAccess(int rd, int rn, const Op2& op2, int size, int flag
                 if (addrIsStatic)
                 {
                     if (staticAddress & 0x3)
-                        ROR_(32, rdMapped, Imm8((staticAddress & 0x3) * 8));
+                        ROR(32, rdMapped, Imm8((staticAddress & 0x3) * 8));
                 }
                 else
                 {
                     AND(32, R(RSCRATCH3), Imm8(0x3));
                     SHL(32, R(RSCRATCH3), Imm8(3));
-                    ROR_(32, rdMapped, R(RSCRATCH3));
+                    ROR(32, rdMapped, R(RSCRATCH3));
                 }
             }
         }
@@ -270,7 +270,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, const Op2& op2, int size, int flag
                 {
                     MOV(32, rdMapped, R(RSCRATCH));
                     if (staticAddress & 0x3)
-                        ROR_(32, rdMapped, Imm8((staticAddress & 0x3) * 8));
+                        ROR(32, rdMapped, Imm8((staticAddress & 0x3) * 8));
                 }
                 else
                 {

src/DMA.cpp

@@ -73,6 +73,8 @@ void DMA::Reset()
     SrcAddrInc = 0;
     DstAddrInc = 0;
 
+    Stall = false;
+
     Running = false;
     InProgress = false;
 
@@ -111,8 +113,8 @@ void DMA::DoSavestate(Savestate* file)
     file->Var32(&DstAddrInc);
 
     file->Var32(&Running);
-    file->Var32((u32*)&InProgress);
+    file->Bool32(&InProgress);
-    file->Var32((u32*)&IsGXFIFODMA);
+    file->Bool32(&IsGXFIFODMA);
 }
 
 void DMA::WriteCnt(u32 val)

src/GPU2D.cpp

@@ -102,6 +102,7 @@ GPU2D::~GPU2D()
 
 void GPU2D::Reset()
 {
+    Enabled = false;
     DispCnt = 0;
     memset(BGCnt, 0, 4*2);
     memset(BGXPos, 0, 4*2);

src/GPU3D.cpp

@@ -470,7 +470,7 @@ void DoSavestate(Savestate* file)
         file->VarArray(vtx->Color, sizeof(s32)*3);
         file->VarArray(vtx->TexCoords, sizeof(s16)*2);
 
-        file->Var32((u32*)&vtx->Clipped);
+        file->Bool32(&vtx->Clipped);
 
         file->VarArray(vtx->FinalPosition, sizeof(s32)*2);
         file->VarArray(vtx->FinalColor, sizeof(s32)*3);
@@ -507,7 +507,7 @@ void DoSavestate(Savestate* file)
         file->VarArray(vtx->Color, sizeof(s32)*3);
         file->VarArray(vtx->TexCoords, sizeof(s16)*2);
 
-        file->Var32((u32*)&vtx->Clipped);
+        file->Bool32(&vtx->Clipped);
 
         file->VarArray(vtx->FinalPosition, sizeof(s32)*2);
         file->VarArray(vtx->FinalColor, sizeof(s32)*3);
@@ -545,17 +545,17 @@ void DoSavestate(Savestate* file)
 
         file->VarArray(poly->FinalZ, sizeof(s32)*10);
         file->VarArray(poly->FinalW, sizeof(s32)*10);
-        file->Var32((u32*)&poly->WBuffer);
+        file->Bool32(&poly->WBuffer);
 
         file->Var32(&poly->Attr);
         file->Var32(&poly->TexParam);
         file->Var32(&poly->TexPalette);
 
-        file->Var32((u32*)&poly->FacingView);
+        file->Bool32(&poly->FacingView);
-        file->Var32((u32*)&poly->Translucent);
+        file->Bool32(&poly->Translucent);
 
-        file->Var32((u32*)&poly->IsShadowMask);
+        file->Bool32(&poly->IsShadowMask);
-        file->Var32((u32*)&poly->IsShadow);
+        file->Bool32(&poly->IsShadow);
 
         if (file->IsAtleastVersion(4, 1))
             file->Var32((u32*)&poly->Type);

src/NDS.cpp

@@ -775,7 +775,7 @@ bool DoSavestate(Savestate* file)
 
     file->Var8(&WRAMCnt);
 
-    file->Var32((u32*)&RunningGame);
+    file->Bool32(&RunningGame);
 
     if (!file->Saving)
     {

src/Savestate.cpp

@@ -261,6 +261,22 @@ void Savestate::Var64(u64* var)
     }
 }
 
+void Savestate::Bool32(bool* var)
+{
+    // for compability
+    if (Saving)
+    {
+        u32 val = *var;
+        Var32(&val);
+    }
+    else
+    {
+        u32 val;
+        Var32(&val);
+        *var = val != 0;
+    }
+}
+
 void Savestate::VarArray(void* data, u32 len)
 {
     if (Error) return;

src/Savestate.h

@@ -46,6 +46,8 @@ public:
     void Var32(u32* var);
     void Var64(u64* var);
 
+    void Bool32(bool* var);
+
     void VarArray(void* data, u32 len);
 
     bool IsAtleastVersion(u32 major, u32 minor)

src/Wifi.cpp

@@ -237,7 +237,7 @@ void DoSavestate(Savestate* file)
 
     file->Var64(&USCounter);
     file->Var64(&USCompare);
-    file->Var32((u32*)&BlockBeaconIRQ14);
+    file->Bool32(&BlockBeaconIRQ14);
 
     file->Var32(&ComStatus);
     file->Var32(&TXCurSlot);

src/dolphin/Arm64Emitter.cpp

@@ -1631,7 +1631,7 @@ void ARM64XEmitter::ASR(ARM64Reg Rd, ARM64Reg Rm, int shift)
   int bits = Is64Bit(Rd) ? 64 : 32;
   SBFM(Rd, Rm, shift, bits - 1);
 }
-void ARM64XEmitter::ROR_(ARM64Reg Rd, ARM64Reg Rm, int shift)
+void ARM64XEmitter::ROR(ARM64Reg Rd, ARM64Reg Rm, int shift)
 {
   EXTR(Rd, Rm, Rm, shift);
 }

src/dolphin/Arm64Emitter.h

@@ -727,7 +727,7 @@ public:
   void LSR(ARM64Reg Rd, ARM64Reg Rm, int shift);
   void LSL(ARM64Reg Rd, ARM64Reg Rm, int shift);
   void ASR(ARM64Reg Rd, ARM64Reg Rm, int shift);
-  void ROR_(ARM64Reg Rd, ARM64Reg Rm, int shift);
+  void ROR(ARM64Reg Rd, ARM64Reg Rm, int shift);
 
   // Logical (immediate)
   void AND(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms, bool invert = false);

src/dolphin/x64Emitter.cpp

@@ -1214,7 +1214,7 @@ void XEmitter::ROL(int bits, const OpArg& dest, const OpArg& shift)
 {
   WriteShift(bits, dest, shift, 0);
 }
-void XEmitter::ROR_(int bits, const OpArg& dest, const OpArg& shift)
+void XEmitter::ROR(int bits, const OpArg& dest, const OpArg& shift)
 {
   WriteShift(bits, dest, shift, 1);
 }

src/dolphin/x64Emitter.h

@@ -489,7 +489,7 @@ public:
 
   // Shift
   void ROL(int bits, const OpArg& dest, const OpArg& shift);
-  void ROR_(int bits, const OpArg& dest, const OpArg& shift);
+  void ROR(int bits, const OpArg& dest, const OpArg& shift);
   void RCL(int bits, const OpArg& dest, const OpArg& shift);
   void RCR(int bits, const OpArg& dest, const OpArg& shift);
   void SHL(int bits, const OpArg& dest, const OpArg& shift);