Slight polish to DMA (#1856)
* Slight polish to DMA - Default-initialize members explicitly - Mark some methods as const noexcept - Initialize DMA::MRAMBurstTable to DMATiming::MRAMDummy - Use the default destructor * Move DMA_Timings definitions to a source file - To ensure constant and unique addresses * Include some extra DMA members in the savestate * Simplify serializing the DMA table - Extend the dummy table to 256 bytes (same length as the real ones) * Revert the type change to DMA::DoSavestate * Keep the MRAMBurstTable inside the DMA class, instead of using a pointer - If we use a pointer to an external table, then we can't use it in savestates (else that external table gets overwritten)
This commit is contained in:
Jesse Talavera-Greenberg
GitHub
parent
bf81b87a60
commit
8c4e5af737
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@ -15,6 +15,7 @@ add_library(core STATIC
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CRC32.cpp
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DMA.cpp
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DMA_Timings.h
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DMA_Timings.cpp
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DSi.cpp
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DSi_AES.cpp
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DSi_Camera.cpp
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16
src/DMA.cpp
16
src/DMA.cpp
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@ -47,21 +47,16 @@ using Platform::LogLevel;
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// TODO: timings are nonseq when address is fixed/decrementing
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DMA::DMA(u32 cpu, u32 num)
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DMA::DMA(u32 cpu, u32 num) :
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CPU(cpu),
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Num(num)
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{
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CPU = cpu;
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Num = num;
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if (cpu == 0)
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CountMask = 0x001FFFFF;
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else
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CountMask = (num==3 ? 0x0000FFFF : 0x00003FFF);
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}
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DMA::~DMA()
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{
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}
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void DMA::Reset()
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{
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SrcAddr = 0;
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@ -82,6 +77,7 @@ void DMA::Reset()
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Executing = false;
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InProgress = false;
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MRAMBurstCount = 0;
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MRAMBurstTable = DMATiming::MRAMDummy;
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}
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void DMA::DoSavestate(Savestate* file)
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@ -106,6 +102,10 @@ void DMA::DoSavestate(Savestate* file)
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file->Bool32(&InProgress);
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file->Bool32(&IsGXFIFODMA);
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file->Var32(&MRAMBurstCount);
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file->Bool32(&Executing);
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file->Bool32(&Stall);
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file->VarArray(MRAMBurstTable.data(), sizeof(MRAMBurstTable));
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}
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void DMA::WriteCnt(u32 val)
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47
src/DMA.h
47
src/DMA.h
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@ -19,14 +19,16 @@
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#ifndef DMA_H
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#define DMA_H
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#include <array>
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#include "types.h"
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#include "Savestate.h"
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#include "DMA_Timings.h"
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class DMA
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{
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public:
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DMA(u32 cpu, u32 num);
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~DMA();
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~DMA() = default;
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void Reset();
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@ -48,12 +50,12 @@ public:
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template <int ConsoleType>
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void Run7();
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bool IsInMode(u32 mode)
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bool IsInMode(u32 mode) const noexcept
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{
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return ((mode == StartMode) && (Cnt & 0x80000000));
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}
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bool IsRunning() { return Running!=0; }
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bool IsRunning() const noexcept { return Running!=0; }
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void StartIfNeeded(u32 mode)
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{
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@ -72,32 +74,33 @@ public:
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if (Executing) Stall = true;
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}
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u32 SrcAddr;
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u32 DstAddr;
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u32 Cnt;
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u32 SrcAddr {};
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u32 DstAddr {};
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u32 Cnt {};
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private:
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u32 CPU, Num;
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u32 CPU {};
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u32 Num {};
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u32 StartMode;
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u32 CurSrcAddr;
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u32 CurDstAddr;
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u32 RemCount;
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u32 IterCount;
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s32 SrcAddrInc;
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s32 DstAddrInc;
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u32 CountMask;
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u32 StartMode {};
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u32 CurSrcAddr {};
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u32 CurDstAddr {};
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u32 RemCount {};
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u32 IterCount {};
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s32 SrcAddrInc {};
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s32 DstAddrInc {};
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u32 CountMask {};
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u32 Running;
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bool InProgress;
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u32 Running {};
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bool InProgress {};
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bool Executing;
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bool Stall;
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bool Executing {};
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bool Stall {};
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bool IsGXFIFODMA;
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bool IsGXFIFODMA {};
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u32 MRAMBurstCount;
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const u8* MRAMBurstTable;
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u32 MRAMBurstCount {};
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std::array<u8, 256> MRAMBurstTable;
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};
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#endif
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@ -0,0 +1,243 @@
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/*
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Copyright 2016-2023 melonDS team
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include "DMA_Timings.h"
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#include "types.h"
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namespace DMATiming
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{
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// DMA timing tables
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//
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// DMA timings on the DS are normally straightforward, except in one case: when
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// main RAM is involved.
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// Main RAM to main RAM is the easy case: 16c/unit in 16bit mode, 18c/unit in 32bit
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// mode.
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// It gets more complicated when transferring from main RAM to somewhere else, or
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// vice versa: main RAM supports burst accesses, but the rules dictating how long
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// bursts can be are weird and inconsistent. Main RAM also supports parallel
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// memory operations, to some extent.
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// I haven't figured out the full logic behind it, let alone how to emulate it
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// efficiently, so for now we will use these tables.
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// A zero denotes the end of a burst pattern.
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//
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// Note: burst patterns only apply when the main RAM address is incrementing.
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// A fixed or decrementing address results in nonsequential accesses.
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//
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// Note about GBA slot/wifi timings: these take into account the sequential timing
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// setting. Timings are such that the nonseq setting only matters for the first
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// access, and minor edge cases (like the last of a 0x20000-byte block).
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extern const std::array<u8, 256> MRAMDummy = {0};
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extern const std::array<u8, 256> MRAMRead16Bursts[] =
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{
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// main RAM to regular 16bit or 32bit bus (similar)
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{7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2,
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7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2,
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7, 3,
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0},
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// main RAM to GBA/wifi, seq=4
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{8, 6, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5,
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0},
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// main RAM to GBA/wifi, seq=6
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{10, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8,
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0},
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};
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extern const std::array<u8, 256> MRAMRead32Bursts[] =
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{
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// main RAM to regular 16bit bus
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{9, 4, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 9,
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0},
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// main RAM to regular 32bit bus
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{9, 3, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2,
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0},
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// main RAM to GBA/wifi, seq=4
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{14, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13,
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0},
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// main RAM to GBA/wifi, seq=6
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{18, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17,
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0},
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};
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extern const std::array<u8, 256> MRAMWrite16Bursts[] =
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{
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// regular 16bit or 32bit bus to main RAM (similar)
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{8, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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0},
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// GBA/wifi to main RAM, seq=4
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{10, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5,
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0},
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// GBA/wifi to main RAM, seq=6
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{9, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7,
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0},
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};
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extern const std::array<u8, 256> MRAMWrite32Bursts[4] =
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{
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// regular 16bit bus to main RAM
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{9, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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0},
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// regular 32bit bus to main RAM
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{9, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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0},
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// GBA/wifi to main RAM, seq=4
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{15, 10, 10, 10, 10, 10, 10, 10, 10, 10,
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10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
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10, 10, 10, 10,
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0},
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// GBA/wifi to main RAM, seq=6
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{16, 14, 14, 14, 14, 14, 14, 14, 14, 14,
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14, 14, 14, 14, 14, 14, 14, 14,
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0},
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};
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}
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@ -19,6 +19,7 @@
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#ifndef DMA_TIMINGS_H
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#define DMA_TIMINGS_H
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#include <array>
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#include "types.h"
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namespace DMATiming
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@ -45,202 +46,15 @@ namespace DMATiming
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// setting. Timings are such that the nonseq setting only matters for the first
|
||||
// access, and minor edge cases (like the last of a 0x20000-byte block).
|
||||
|
||||
constexpr u8 MRAMDummy[1] = {0};
|
||||
extern const std::array<u8, 256> MRAMDummy;
|
||||
|
||||
constexpr u8 MRAMRead16Bursts[][256] =
|
||||
{
|
||||
// main RAM to regular 16bit or 32bit bus (similar)
|
||||
{7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
7, 3,
|
||||
0},
|
||||
// main RAM to GBA/wifi, seq=4
|
||||
{8, 6, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5,
|
||||
0},
|
||||
// main RAM to GBA/wifi, seq=6
|
||||
{10, 8, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7,
|
||||
12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7,
|
||||
12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7,
|
||||
12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7,
|
||||
12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7,
|
||||
12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7,
|
||||
12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7,
|
||||
12, 8,
|
||||
0},
|
||||
};
|
||||
extern const std::array<u8, 256> MRAMRead16Bursts[3];
|
||||
|
||||
constexpr u8 MRAMRead32Bursts[][256] =
|
||||
{
|
||||
// main RAM to regular 16bit bus
|
||||
{9, 4, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 9,
|
||||
0},
|
||||
// main RAM to regular 32bit bus
|
||||
{9, 3, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2,
|
||||
0},
|
||||
// main RAM to GBA/wifi, seq=4
|
||||
{14, 10, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9,
|
||||
13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9,
|
||||
13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9,
|
||||
13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9,
|
||||
13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
|
||||
9, 9, 9, 9, 9, 9, 9,
|
||||
13,
|
||||
0},
|
||||
// main RAM to GBA/wifi, seq=6
|
||||
{18, 14, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
13, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
13, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
13, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
13, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
13, 13, 13, 13, 13, 13, 13, 13, 13,
|
||||
17,
|
||||
0},
|
||||
};
|
||||
extern const std::array<u8, 256> MRAMRead32Bursts[4];
|
||||
|
||||
constexpr u8 MRAMWrite16Bursts[][256] =
|
||||
{
|
||||
// regular 16bit or 32bit bus to main RAM (similar)
|
||||
{8, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
0},
|
||||
// GBA/wifi to main RAM, seq=4
|
||||
{10, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
|
||||
5, 5, 5, 5, 5, 5, 5, 5,
|
||||
0},
|
||||
// GBA/wifi to main RAM, seq=6
|
||||
{9, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 7,
|
||||
0},
|
||||
};
|
||||
extern const std::array<u8, 256> MRAMWrite16Bursts[3];
|
||||
|
||||
constexpr u8 MRAMWrite32Bursts[][256] =
|
||||
{
|
||||
// regular 16bit bus to main RAM
|
||||
{9, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
||||
4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
||||
4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
||||
4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
||||
4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
||||
4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
||||
0},
|
||||
// regular 32bit bus to main RAM
|
||||
{9, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
0},
|
||||
// GBA/wifi to main RAM, seq=4
|
||||
{15, 10, 10, 10, 10, 10, 10, 10, 10, 10,
|
||||
10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
|
||||
10, 10, 10, 10,
|
||||
0},
|
||||
// GBA/wifi to main RAM, seq=6
|
||||
{16, 14, 14, 14, 14, 14, 14, 14, 14, 14,
|
||||
14, 14, 14, 14, 14, 14, 14, 14,
|
||||
0},
|
||||
};
|
||||
extern const std::array<u8, 256> MRAMWrite32Bursts[4];
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#include "types.h"
|
||||
|
||||
#define SAVESTATE_MAJOR 10
|
||||
#define SAVESTATE_MINOR 0
|
||||
#define SAVESTATE_MINOR 1
|
||||
|
||||
class Savestate
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue