Arisotura
parent
8c64290958
commit
851e255b40
36
src/DSi.cpp
36
src/DSi.cpp
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@ -44,6 +44,8 @@ namespace DSi
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u32 BootAddr[2];
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u16 SCFG_Clock9;
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u16 SCFG_Clock7;
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u32 SCFG_MC;
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u32 MBK[2][9];
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@ -123,11 +125,19 @@ void Reset()
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SDMMC->Reset();
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SDIO->Reset();
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SCFG_Clock9 = 0x0187; // CHECKME
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SCFG_Clock7 = 0x0187;
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SCFG_MC = 0x0011;
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// LCD init flag
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GPU::DispStat[0] |= (1<<6);
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GPU::DispStat[1] |= (1<<6);
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NDS::MapSharedWRAM(3);
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// TEST
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u8 derp[16] = {0xE5, 0xCC, 0x5A, 0x8B, 0x56, 0xD0, 0xC9, 0x72, 0x9C, 0x17, 0xE8, 0xDC, 0x39, 0x12, 0x36, 0xA9};
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for (int i = 0; i < 16; i+=4) ARM7Write32(0x03FFC580+i, *(u32*)&derp[i]);
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}
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bool LoadBIOS()
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@ -1007,7 +1017,7 @@ u16 ARM9IORead16(u32 addr)
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{
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switch (addr)
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{
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case 0x04004004: return 0; // TODO
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case 0x04004004: return SCFG_Clock9;
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case 0x04004010: return SCFG_MC & 0xFFFF;
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CASE_READ16_32BIT(0x04004040, MBK[0][0])
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@ -1079,6 +1089,16 @@ void ARM9IOWrite8(u32 addr, u8 val)
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{
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switch (addr)
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{
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case 0x04000301:
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// TODO: OPTIONAL PERFORMANCE HACK
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// the DSi ARM9 BIOS has a bug where the IRQ wait function attempts to use (ARM7-only) HALTCNT
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// effectively causing it to wait in a busy loop.
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// for better DSi performance, we can implement an actual IRQ wait here.
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// in practice this would only matter when running DS software in DSi mode (ie already a hack).
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// DSi software does not use the BIOS IRQ wait function.
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//if (val == 0x80 && NDS::ARM9->R[15] == 0xFFFF0268) NDS::ARM9->Halt(1);
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return;
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case 0x04004040: MapNWRAM_A(0, val); return;
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case 0x04004041: MapNWRAM_A(1, val); return;
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case 0x04004042: MapNWRAM_A(2, val); return;
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@ -1108,6 +1128,12 @@ void ARM9IOWrite16(u32 addr, u16 val)
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{
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switch (addr)
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{
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case 0x04004004:
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// TODO: actually change clock!
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printf("CLOCK9=%04X\n", val);
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SCFG_Clock9 = val & 0x0187;
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return;
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case 0x04004040:
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MapNWRAM_A(0, val & 0xFF);
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MapNWRAM_A(1, val >> 8);
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@ -1267,7 +1293,7 @@ u16 ARM7IORead16(u32 addr)
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case 0x04000218: return NDS::IE2;
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case 0x0400021C: return NDS::IF2;
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case 0x04004004: return 0x0187;
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case 0x04004004: return SCFG_Clock7;
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case 0x04004006: return 0; // JTAG register
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case 0x04004010: return SCFG_MC & 0xFFFF;
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@ -1390,6 +1416,10 @@ void ARM7IOWrite16(u32 addr, u16 val)
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case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return;
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case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return;
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case 0x04004004:
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SCFG_Clock7 = val & 0x0187;
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return;
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case 0x04004010:
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val &= 0x800C;
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if ((val & 0xC) == 0xC) val &= ~0xC; // hax
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@ -1482,7 +1512,7 @@ void ARM7IOWrite32(u32 addr, u32 val)
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{
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addr -= 0x04004440;
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int n = 0;
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while (addr > 0x30) { addr -= 0x30; n++; }
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while (addr >= 0x30) { addr -= 0x30; n++; }
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switch (addr >> 4)
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{
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134
src/DSi_AES.cpp
134
src/DSi_AES.cpp
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@ -42,11 +42,14 @@ FIFO<u32>* OutputFIFO;
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u8 IV[16];
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u8 MAC[16];
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u8 KeyNormal[4][16];
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u8 KeyX[4][16];
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u8 KeyY[4][16];
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u8 CurKey[16];
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u8 CurMAC[16];
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AES_ctx Ctx;
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@ -77,6 +80,9 @@ void ROL16(u8* val, u32 n)
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#define _printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); }
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#define _printhex2(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); }
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#define _printhexR(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[((size)-1)-z]); printf("\n"); }
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#define _printhex2R(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[((size)-1)-z]); }
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bool Init()
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{
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@ -111,11 +117,16 @@ void Reset()
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InputFIFO->Clear();
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OutputFIFO->Clear();
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memset(IV, 0, sizeof(IV));
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memset(MAC, 0, sizeof(MAC));
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memset(KeyNormal, 0, sizeof(KeyNormal));
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memset(KeyX, 0, sizeof(KeyX));
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memset(KeyY, 0, sizeof(KeyY));
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memset(CurKey, 0, sizeof(CurKey));
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memset(CurMAC, 0, sizeof(CurMAC));
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// initialize keys, as per GBAtek
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@ -123,6 +134,12 @@ void Reset()
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*(u32*)&KeyX[0][0] = 0x746E694E;
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*(u32*)&KeyX[0][4] = 0x6F646E65;
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// slot 1: 'Tad'/dev.kp
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*(u32*)&KeyX[1][0] = 0x4E00004A;
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*(u32*)&KeyX[1][4] = 0x4A00004E;
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*(u32*)&KeyX[1][8] = (u32)(DSi::ConsoleID >> 32) ^ 0xC80C4B72;
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*(u32*)&KeyX[1][12] = (u32)DSi::ConsoleID;
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// slot 3: console-unique eMMC crypto
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*(u32*)&KeyX[3][0] = (u32)DSi::ConsoleID;
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*(u32*)&KeyX[3][4] = (u32)DSi::ConsoleID ^ 0x24EE6906;
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@ -134,6 +151,34 @@ void Reset()
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}
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void ProcessBlock_CCM_Decrypt()
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{
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u8 data[16];
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u8 data_rev[16];
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*(u32*)&data[0] = InputFIFO->Read();
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*(u32*)&data[4] = InputFIFO->Read();
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*(u32*)&data[8] = InputFIFO->Read();
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*(u32*)&data[12] = InputFIFO->Read();
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//printf("AES-CCM: "); _printhex2(data, 16);
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Swap16(data_rev, data);
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AES_CTR_xcrypt_buffer(&Ctx, data_rev, 16);
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for (int i = 0; i < 16; i++) CurMAC[i] ^= data_rev[i];
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AES_ECB_encrypt(&Ctx, CurMAC);
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Swap16(data, data_rev);
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//printf(" -> "); _printhex2(data, 16);
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OutputFIFO->Write(*(u32*)&data[0]);
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OutputFIFO->Write(*(u32*)&data[4]);
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OutputFIFO->Write(*(u32*)&data[8]);
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OutputFIFO->Write(*(u32*)&data[12]);
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}
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void ProcessBlock_CTR()
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{
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u8 data[16];
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@ -186,18 +231,12 @@ void WriteCnt(u32 val)
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OutputDMASize = dmasize_out[(val >> 14) & 0x3];
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AESMode = (val >> 28) & 0x3;
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if (AESMode < 2) printf("AES-CCM TODO\n");
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if (AESMode == 1) printf("AES-CCM TODO\n");
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if (val & (1<<24))
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{
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u32 slot = (val >> 26) & 0x3;
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memcpy(CurKey, KeyNormal[slot], 16);
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//printf("AES: key(%d): ", slot); _printhex(CurKey, 16);
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u8 tmp[16];
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Swap16(tmp, CurKey);
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AES_init_ctx(&Ctx, tmp);
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}
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if (!(oldcnt & (1<<31)) && (val & (1<<31)))
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@ -205,11 +244,45 @@ void WriteCnt(u32 val)
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// transfer start (checkme)
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RemBlocks = BlkCnt >> 16;
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u8 key[16];
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u8 iv[16];
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Swap16(key, CurKey);
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Swap16(iv, IV);
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if (AESMode < 2)
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{
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if (BlkCnt & 0xFFFF) printf("AES: CCM EXTRA LEN TODO\n");
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u32 maclen = (val >> 16) & 0x7;
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if (maclen < 1) maclen = 1;
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iv[0] = 0x02;
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for (int i = 0; i < 12; i++) iv[1+i] = iv[4+i];
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iv[13] = 0x00;
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iv[14] = 0x00;
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iv[15] = 0x01;
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AES_init_ctx_iv(&Ctx, key, iv);
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iv[0] |= (maclen << 3) | ((BlkCnt & 0xFFFF) ? (1<<6) : 0);
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iv[13] = RemBlocks >> 12;
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iv[14] = RemBlocks >> 4;
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iv[15] = RemBlocks << 4;
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memcpy(CurMAC, iv, 16);
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AES_ECB_encrypt(&Ctx, CurMAC);
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}
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else
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{
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AES_init_ctx_iv(&Ctx, key, iv);
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}
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DSi::CheckNDMAs(1, 0x2A);
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}
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printf("AES CNT: %08X / mode=%d inDMA=%d outDMA=%d blocks=%d\n",
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val, AESMode, InputDMASize, OutputDMASize, RemBlocks);
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printf("AES CNT: %08X / mode=%d key=%d inDMA=%d outDMA=%d blocks=%d\n",
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val, AESMode, (val >> 26) & 0x3, InputDMASize, OutputDMASize, RemBlocks);
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}
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void WriteBlkCnt(u32 val)
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@ -219,6 +292,8 @@ void WriteBlkCnt(u32 val)
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u32 ReadOutputFIFO()
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{
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if (OutputFIFO->IsEmpty()) printf("!!! AES OUTPUT FIFO EMPTY\n");
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u32 ret = OutputFIFO->Read();
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if (Cnt & (1<<31))
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@ -241,6 +316,8 @@ void WriteInputFIFO(u32 val)
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{
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// TODO: add some delay to processing
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if (InputFIFO->IsFull()) printf("!!! AES INPUT FIFO FULL\n");
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InputFIFO->Write(val);
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if (!(Cnt & (1<<31))) return;
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@ -276,6 +353,7 @@ void Update()
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{
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switch (AESMode)
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{
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case 0: ProcessBlock_CCM_Decrypt(); break;
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case 2:
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case 3: ProcessBlock_CTR(); break;
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default:
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@ -293,6 +371,28 @@ void Update()
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if (RemBlocks == 0)
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{
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if (AESMode == 0)
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{
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Ctx.Iv[13] = 0x00;
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Ctx.Iv[14] = 0x00;
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Ctx.Iv[15] = 0x00;_printhex(Ctx.Iv, 16);
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AES_CTR_xcrypt_buffer(&Ctx, CurMAC, 16);
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//printf("FINAL MAC: "); _printhexR(CurMAC, 16);
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//printf("INPUT MAC: "); _printhex(MAC, 16);
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Cnt |= (1<<21);
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for (int i = 0; i < 16; i++)
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{
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if (CurMAC[15-i] != MAC[i]) Cnt &= ~(1<<21);
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}
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}
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else
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{
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// CHECKME
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Cnt &= ~(1<<21);
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}
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Cnt &= ~(1<<31);
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if (Cnt & (1<<30)) NDS::SetIRQ2(NDS::IRQ2_DSi_AES);
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DSi::StopNDMAs(1, 0x2A);
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@ -313,15 +413,15 @@ void WriteIV(u32 offset, u32 val, u32 mask)
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*(u32*)&IV[offset] = (old & ~mask) | (val & mask);
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//printf("AES: IV: "); _printhex(IV, 16);
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u8 tmp[16];
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Swap16(tmp, IV);
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AES_ctx_set_iv(&Ctx, tmp);
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}
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void WriteMAC(u32 offset, u32 val, u32 mask)
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{
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//
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u32 old = *(u32*)&MAC[offset];
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*(u32*)&MAC[offset] = (old & ~mask) | (val & mask);
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//printf("AES: MAC: "); _printhex(MAC, 16);
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}
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void DeriveNormalKey(u32 slot)
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@ -355,6 +455,8 @@ void WriteKeyNormal(u32 slot, u32 offset, u32 val, u32 mask)
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u32 old = *(u32*)&KeyNormal[slot][offset];
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*(u32*)&KeyNormal[slot][offset] = (old & ~mask) | (val & mask);
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//printf("KeyNormal(%d): ", slot); _printhex(KeyNormal[slot], 16);
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}
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void WriteKeyX(u32 slot, u32 offset, u32 val, u32 mask)
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@ -362,6 +464,8 @@ void WriteKeyX(u32 slot, u32 offset, u32 val, u32 mask)
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u32 old = *(u32*)&KeyX[slot][offset];
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*(u32*)&KeyX[slot][offset] = (old & ~mask) | (val & mask);
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//printf("KeyX(%d): ", slot); _printhex(KeyX[slot], 16);
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}
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void WriteKeyY(u32 slot, u32 offset, u32 val, u32 mask)
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@ -370,6 +474,8 @@ void WriteKeyY(u32 slot, u32 offset, u32 val, u32 mask)
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*(u32*)&KeyY[slot][offset] = (old & ~mask) | (val & mask);
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//printf("[%08X] KeyY(%d): ", NDS::GetPC(1), slot); _printhex(KeyY[slot], 16);
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if (offset >= 0xC)
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{
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DeriveNormalKey(slot);
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@ -123,7 +123,10 @@ void DSi_NDMA::Start()
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if (((StartMode & 0x1F) != 0x10) && !(Cnt & (1<<29)))
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{
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if (IterCount > TotalRemCount)
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{
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IterCount = TotalRemCount;
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RemCount = IterCount;
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}
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}
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if (Cnt & (1<<12)) CurDstAddr = DstAddr;
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@ -185,6 +185,17 @@ void DSi_SDHost::SendData(u8* data, u32 len)
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NDS::ScheduleEvent(NDS::Event_DSi_SDTransfer, false, 512, FinishSend, param);
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}
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void DSi_SDHost::FinishReceive(u32 param)
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{
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DSi_SDHost* host = (param & 0x1) ? DSi::SDIO : DSi::SDMMC;
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DSi_SDDevice* dev = host->Ports[host->PortSelect & 0x1];
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host->ClearIRQ(24);
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host->SetIRQ(25);
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if (dev) dev->ContinueTransfer();
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}
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void DSi_SDHost::ReceiveData(u8* data, u32 len)
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{
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printf("%s: data TX, len=%d, blkcnt=%d (%d) blklen=%d, irq=%08X\n", SD_DESC, len, BlockCount16, BlockCountInternal, BlockLen16, IRQMask);
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@ -481,10 +492,12 @@ void DSi_SDHost::WriteFIFO32(u32 val)
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// we completed one block, send it to the SD card
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ClearIRQ(24);
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SetIRQ(25);
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//ClearIRQ(24);
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//SetIRQ(25);
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if (dev) dev->ContinueTransfer();
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//if (dev) dev->ContinueTransfer();
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// TODO measure the actual delay!!
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NDS::ScheduleEvent(NDS::Event_DSi_SDTransfer, false, 2048, FinishReceive, Num);
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}
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@ -622,10 +635,10 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param)
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Host->SendResponse(CSR, true);
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WriteBlock(RWAddress);
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RWAddress += BlockSize;
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SetState(0x06);
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SetState(0x04);
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return;
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case 55: // ??
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case 55: // appcmd prefix
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CSR |= (1<<5);
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Host->SendResponse(CSR, true);
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return;
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@ -37,6 +37,7 @@ public:
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void DoSavestate(Savestate* file);
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static void FinishSend(u32 param);
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static void FinishReceive(u32 param);
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void SendResponse(u32 val, bool last);
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void SendData(u8* data, u32 len);
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void ReceiveData(u8* data, u32 len);
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@ -19,6 +19,7 @@
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#include <stdio.h>
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#include <string.h>
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#include "NDS.h"
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#include "DSi.h"
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#include "SPU.h"
|
||||
|
||||
|
||||
|
|
@ -216,7 +217,8 @@ void Channel::FIFO_BufferData()
|
|||
|
||||
for (u32 i = 0; i < burstlen; i += 4)
|
||||
{
|
||||
FIFO[FIFOWritePos] = NDS::ARM7Read32(SrcAddr + FIFOReadOffset);
|
||||
//FIFO[FIFOWritePos] = NDS::ARM7Read32(SrcAddr + FIFOReadOffset);
|
||||
FIFO[FIFOWritePos] = DSi::ARM7Read32(SrcAddr + FIFOReadOffset);
|
||||
FIFOReadOffset += 4;
|
||||
FIFOWritePos++;
|
||||
FIFOWritePos &= 0x7;
|
||||
|
|
@ -499,7 +501,8 @@ void CaptureUnit::FIFO_FlushData()
|
|||
{
|
||||
for (u32 i = 0; i < 4; i++)
|
||||
{
|
||||
NDS::ARM7Write32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]);
|
||||
//NDS::ARM7Write32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]);
|
||||
DSi::ARM7Write32(DstAddr + FIFOWriteOffset, FIFO[FIFOReadPos]);
|
||||
|
||||
FIFOReadPos++;
|
||||
FIFOReadPos &= 0x3;
|
||||
|
|
|
|||
Loading…
Reference in New Issue