more accurate dcache timing?
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993048dd24
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@ -223,6 +223,11 @@ public:
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void CP15Write(u32 id, u32 val);
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void CP15Write(u32 id, u32 val);
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u32 CP15Read(u32 id);
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u32 CP15Read(u32 id);
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void CalcDCacheCycles(u32 addr);
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u32 DCacheCurIndex = 0;
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u32 DCacheHistory[32] = {0};
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u64 DCacheHistorySum = 0;
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u32 CP15Control;
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u32 CP15Control;
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u32 RNGSeed;
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u32 RNGSeed;
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65
src/CP15.cpp
65
src/CP15.cpp
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@ -27,12 +27,19 @@
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// this was measured to be close to hardware average
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// this was measured to be close to hardware average
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// a value of 1 would represent a perfect cache, but that causes
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// a value of 1 would represent a perfect cache, but that causes
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// games to run too fast, causing a number of issues
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// games to run too fast, causing a number of issues
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const int kDataCacheTiming = 3;//2;
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const int kDataCacheTiming = 1;//2;
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const int kDataCacheTimingSlow = 17;
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const int kCodeCacheTiming = 3;//5;
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const int kCodeCacheTiming = 3;//5;
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u64 sumDataCacheCycles = 0;
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u64 dataCacheInstrsCount = 0;
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void ARMv5::CP15Reset()
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void ARMv5::CP15Reset()
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{
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{
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printf("avg. %f\n", (float)sumDataCacheCycles/(float)dataCacheInstrsCount);
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sumDataCacheCycles = 0;
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dataCacheInstrsCount = 0;
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CP15Control = 0x2078; // dunno
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CP15Control = 0x2078; // dunno
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RNGSeed = 44203;
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RNGSeed = 44203;
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@ -277,8 +284,8 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
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if (pu & 0x10)
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if (pu & 0x10)
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{
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{
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MemTimings[i][1] = kDataCacheTiming;
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MemTimings[i][1] = 0xFF;
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MemTimings[i][2] = kDataCacheTiming;
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MemTimings[i][2] = 0xFF;
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MemTimings[i][3] = 1;
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MemTimings[i][3] = 1;
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}
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}
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else
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else
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@ -291,6 +298,28 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
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}
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}
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void ARMv5::CalcDCacheCycles(u32 addr)
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{
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u64 prevAvg = DCacheHistorySum / 32;
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DCacheHistorySum -= DCacheHistory[DCacheCurIndex];
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DCacheHistory[DCacheCurIndex] = addr & ~0x1F;
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DCacheHistorySum += DCacheHistory[DCacheCurIndex];
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u64 curAvg = DCacheHistorySum / 32;
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u64 diff = abs((s64)curAvg - (s64)prevAvg);
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if (diff > 3)
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DataCycles = kDataCacheTimingSlow;
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else
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DataCycles = kDataCacheTiming;
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dataCacheInstrsCount++;
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sumDataCacheCycles += DataCycles;
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DCacheCurIndex++;
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DCacheCurIndex &= 0x1F;
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}
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u32 ARMv5::RandomLineIndex()
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u32 ARMv5::RandomLineIndex()
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{
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{
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// lame RNG, but good enough for this purpose
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// lame RNG, but good enough for this purpose
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@ -740,6 +769,11 @@ void ARMv5::DataRead8(u32 addr, u32* val)
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*val = NDS::ARM9Read8(addr);
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*val = NDS::ARM9Read8(addr);
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DataCycles = MemTimings[addr >> 12][1];
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DataCycles = MemTimings[addr >> 12][1];
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if (DataCycles == 0xFF)
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{
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CalcDCacheCycles(addr);
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}
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}
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}
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void ARMv5::DataRead16(u32 addr, u32* val)
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void ARMv5::DataRead16(u32 addr, u32* val)
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@ -761,6 +795,11 @@ void ARMv5::DataRead16(u32 addr, u32* val)
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*val = NDS::ARM9Read16(addr);
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*val = NDS::ARM9Read16(addr);
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DataCycles = MemTimings[addr >> 12][1];
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DataCycles = MemTimings[addr >> 12][1];
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if (DataCycles == 0xFF)
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{
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CalcDCacheCycles(addr);
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}
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}
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}
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void ARMv5::DataRead32(u32 addr, u32* val)
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void ARMv5::DataRead32(u32 addr, u32* val)
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@ -782,6 +821,11 @@ void ARMv5::DataRead32(u32 addr, u32* val)
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*val = NDS::ARM9Read32(addr);
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*val = NDS::ARM9Read32(addr);
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DataCycles = MemTimings[addr >> 12][2];
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DataCycles = MemTimings[addr >> 12][2];
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if (DataCycles == 0xFF)
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{
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CalcDCacheCycles(addr);
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}
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}
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}
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void ARMv5::DataRead32S(u32 addr, u32* val)
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void ARMv5::DataRead32S(u32 addr, u32* val)
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@ -822,6 +866,11 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
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NDS::ARM9Write8(addr, val);
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NDS::ARM9Write8(addr, val);
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DataCycles = MemTimings[addr >> 12][1];
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DataCycles = MemTimings[addr >> 12][1];
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if (DataCycles == 0xFF)
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{
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CalcDCacheCycles(addr);
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}
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}
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}
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void ARMv5::DataWrite16(u32 addr, u16 val)
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void ARMv5::DataWrite16(u32 addr, u16 val)
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@ -843,6 +892,11 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
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NDS::ARM9Write16(addr, val);
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NDS::ARM9Write16(addr, val);
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DataCycles = MemTimings[addr >> 12][1];
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DataCycles = MemTimings[addr >> 12][1];
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if (DataCycles == 0xFF)
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{
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CalcDCacheCycles(addr);
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}
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}
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}
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void ARMv5::DataWrite32(u32 addr, u32 val)
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void ARMv5::DataWrite32(u32 addr, u32 val)
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@ -864,6 +918,11 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
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NDS::ARM9Write32(addr, val);
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NDS::ARM9Write32(addr, val);
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DataCycles = MemTimings[addr >> 12][2];
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DataCycles = MemTimings[addr >> 12][2];
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if (DataCycles == 0xFF)
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{
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CalcDCacheCycles(addr);
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}
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}
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}
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void ARMv5::DataWrite32S(u32 addr, u32 val)
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void ARMv5::DataWrite32S(u32 addr, u32 val)
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