fix bug with ALU operations and shift operands, where the shift operation could obliterate the carry flag
also, misc shit
This commit is contained in:
StapleButter
parent
3e5e8f60c4
commit
7dba0121cb
34
ARM.cpp
34
ARM.cpp
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@ -290,6 +290,40 @@ s32 ARM::Execute(s32 cycles)
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TriggerIRQ();
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}
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// R1=X R2=Y
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//if (R[15]==0x02328E88)
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// printf("hah! %04X %08X %08X %08X\n", Read16(R[0]+4), R[1], R[2],
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// Read32(R[13]+0x18+16+4));
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/*if (R[15]==0x02328DA6)
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printf("derpo %08X %08X %08X %08X %08X %08X | %08X\n", R[0], R[1], R[2], R[3],
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Read32(R[13]+0x40+0), Read32(R[13]+0x40+4), R[14]);*/
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/*if (R[15]==0x02328C64)
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printf("derpo %08X %08X %08X %08X %08X %08X %08X %08X | %08X | %04X %04X\n", R[0], R[1], R[2], R[3],
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Read32(R[13]+0x40+0), Read32(R[13]+0x40+4), Read32(R[13]+0x40+8), Read32(R[13]+0x40+12), R[14],
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Read16(R[0]+8), Read16(R[0]+12));*/
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/*if (R[15]==0x023290B2)
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printf("derpo %08X %08X %08X %08X | %08X\n", R[0], R[1], R[2], R[3],
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R[14]);
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if (R[15]==0x23290DE)
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printf("!!!!! %08X %04X %04X %08X %08X %08X %08X\n", R[3], Read16(R[3]), Read16(R[3]+2), R[2],
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Read32(0x023A6184+0), Read32(0x023A6184+4), Read32(0x023A6184+8));
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if (R[15]==0x23290EA)
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printf("!!!!! %08X %08X\n", R[2], R[3]);
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if (R[15]==0x2328C80)
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printf("STRING SIZE=%08X\n", R[0]);
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if (R[15]==0x2328CC2)
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printf("SUMLOL=%08X %08X %08X\n", R[4], R[7], R[0]);
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if (R[15]==0x2328CC8)
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printf("SUM=%08X %08X %08X\n", R[4], R[7], R[0]);
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if (R[15]>=0x2328D6C && R[15]<=0x2328D9C)
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printf("%08X CALC %08X %08X\n", R[15]-4, R[0], R[1]);
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if (R[15]>=0x232CCCC && R[15]<=0x232CED4)
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printf("%08X DIV %08X %08X %08X %08X carry %d\n", R[15]-4, R[0], R[1], R[2], R[3], (CPSR&0x20000000)?1:0);*/
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// temp. debug cruft
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addr = R[15] - (CPSR&0x20 ? 4:8);
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cpsr = CPSR;
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@ -137,7 +137,7 @@ namespace ARMInterpreter
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shiftop(b, cpu->R[(cpu->CurInstr>>8)&0xF]);
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#define A_IMPLEMENT_ALU_OP(x) \
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#define A_IMPLEMENT_ALU_OP(x,s) \
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\
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s32 A_##x##_IMM(ARM* cpu) \
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{ \
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@ -191,46 +191,46 @@ s32 A_##x##_IMM_S(ARM* cpu) \
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} \
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s32 A_##x##_REG_LSL_IMM_S(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM_S) \
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A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM##s) \
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A_##x##_S(0) \
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} \
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s32 A_##x##_REG_LSR_IMM_S(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM_S) \
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A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM##s) \
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A_##x##_S(0) \
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} \
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s32 A_##x##_REG_ASR_IMM_S(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM_S) \
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A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM##s) \
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A_##x##_S(0) \
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} \
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s32 A_##x##_REG_ROR_IMM_S(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM_S) \
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A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM##s) \
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A_##x##_S(0) \
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} \
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s32 A_##x##_REG_LSL_REG_S(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_REG(LSL_REG_S) \
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A_CALC_OP2_REG_SHIFT_REG(LSL_REG##s) \
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A_##x##_S(1) \
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} \
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s32 A_##x##_REG_LSR_REG_S(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_REG(LSR_REG_S) \
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A_CALC_OP2_REG_SHIFT_REG(LSR_REG##s) \
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A_##x##_S(1) \
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} \
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s32 A_##x##_REG_ASR_REG_S(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_REG(ASR_REG_S) \
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A_CALC_OP2_REG_SHIFT_REG(ASR_REG##s) \
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A_##x##_S(1) \
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} \
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s32 A_##x##_REG_ROR_REG_S(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_REG(ROR_REG_S) \
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A_CALC_OP2_REG_SHIFT_REG(ROR_REG##s) \
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A_##x##_S(1) \
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}
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#define A_IMPLEMENT_ALU_TEST(x) \
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#define A_IMPLEMENT_ALU_TEST(x,s) \
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\
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s32 A_##x##_IMM(ARM* cpu) \
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{ \
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@ -239,42 +239,42 @@ s32 A_##x##_IMM(ARM* cpu) \
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} \
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s32 A_##x##_REG_LSL_IMM(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM_S) \
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A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM##s) \
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A_##x(0) \
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} \
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s32 A_##x##_REG_LSR_IMM(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM_S) \
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A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM##s) \
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A_##x(0) \
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} \
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s32 A_##x##_REG_ASR_IMM(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM_S) \
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A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM##s) \
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A_##x(0) \
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} \
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s32 A_##x##_REG_ROR_IMM(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM_S) \
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A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM##s) \
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A_##x(0) \
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} \
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s32 A_##x##_REG_LSL_REG(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_REG(LSL_REG_S) \
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A_CALC_OP2_REG_SHIFT_REG(LSL_REG##s) \
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A_##x(1) \
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} \
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s32 A_##x##_REG_LSR_REG(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_REG(LSR_REG_S) \
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A_CALC_OP2_REG_SHIFT_REG(LSR_REG##s) \
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A_##x(1) \
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} \
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s32 A_##x##_REG_ASR_REG(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_REG(ASR_REG_S) \
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A_CALC_OP2_REG_SHIFT_REG(ASR_REG##s) \
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A_##x(1) \
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} \
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s32 A_##x##_REG_ROR_REG(ARM* cpu) \
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{ \
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A_CALC_OP2_REG_SHIFT_REG(ROR_REG_S) \
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A_CALC_OP2_REG_SHIFT_REG(ROR_REG##s) \
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A_##x(1) \
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}
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@ -309,7 +309,7 @@ s32 A_##x##_REG_ROR_REG(ARM* cpu) \
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(AND)
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A_IMPLEMENT_ALU_OP(AND,_S)
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#define A_EOR(c) \
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@ -342,7 +342,7 @@ A_IMPLEMENT_ALU_OP(AND)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(EOR)
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A_IMPLEMENT_ALU_OP(EOR,_S)
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#define A_SUB(c) \
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@ -377,7 +377,7 @@ A_IMPLEMENT_ALU_OP(EOR)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(SUB)
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A_IMPLEMENT_ALU_OP(SUB,)
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#define A_RSB(c) \
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@ -412,7 +412,7 @@ A_IMPLEMENT_ALU_OP(SUB)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(RSB)
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A_IMPLEMENT_ALU_OP(RSB,)
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#define A_ADD(c) \
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@ -447,7 +447,7 @@ A_IMPLEMENT_ALU_OP(RSB)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(ADD)
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A_IMPLEMENT_ALU_OP(ADD,)
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#define A_ADC(c) \
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@ -484,7 +484,7 @@ A_IMPLEMENT_ALU_OP(ADD)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(ADC)
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A_IMPLEMENT_ALU_OP(ADC,)
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#define A_SBC(c) \
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@ -521,7 +521,7 @@ A_IMPLEMENT_ALU_OP(ADC)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(SBC)
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A_IMPLEMENT_ALU_OP(SBC,)
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#define A_RSC(c) \
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@ -558,7 +558,7 @@ A_IMPLEMENT_ALU_OP(SBC)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(RSC)
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A_IMPLEMENT_ALU_OP(RSC,)
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#define A_TST(c) \
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@ -568,7 +568,7 @@ A_IMPLEMENT_ALU_OP(RSC)
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!res); \
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return C_S(1) + C_I(c);
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A_IMPLEMENT_ALU_TEST(TST)
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A_IMPLEMENT_ALU_TEST(TST,_S)
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#define A_TEQ(c) \
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@ -578,7 +578,7 @@ A_IMPLEMENT_ALU_TEST(TST)
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!res); \
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return C_S(1) + C_I(c);
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A_IMPLEMENT_ALU_TEST(TEQ)
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A_IMPLEMENT_ALU_TEST(TEQ,_S)
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#define A_CMP(c) \
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@ -590,7 +590,7 @@ A_IMPLEMENT_ALU_TEST(TEQ)
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OVERFLOW_SUB(a, b, res)); \
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return C_S(1) + C_I(c);
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A_IMPLEMENT_ALU_TEST(CMP)
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A_IMPLEMENT_ALU_TEST(CMP,)
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#define A_CMN(c) \
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@ -602,7 +602,7 @@ A_IMPLEMENT_ALU_TEST(CMP)
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OVERFLOW_ADD(a, b, res)); \
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return C_S(1) + C_I(c);
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A_IMPLEMENT_ALU_TEST(CMN)
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A_IMPLEMENT_ALU_TEST(CMN,)
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#define A_ORR(c) \
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@ -635,7 +635,7 @@ A_IMPLEMENT_ALU_TEST(CMN)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(ORR)
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A_IMPLEMENT_ALU_OP(ORR,_S)
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#define A_MOV(c) \
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@ -664,7 +664,7 @@ A_IMPLEMENT_ALU_OP(ORR)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(MOV)
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A_IMPLEMENT_ALU_OP(MOV,_S)
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#define A_BIC(c) \
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@ -697,7 +697,7 @@ A_IMPLEMENT_ALU_OP(MOV)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(BIC)
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A_IMPLEMENT_ALU_OP(BIC,_S)
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#define A_MVN(c) \
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@ -728,7 +728,7 @@ A_IMPLEMENT_ALU_OP(BIC)
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return C_S(1) + C_I(c); \
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}
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A_IMPLEMENT_ALU_OP(MVN)
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A_IMPLEMENT_ALU_OP(MVN,_S)
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2
DMA.cpp
2
DMA.cpp
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@ -106,7 +106,7 @@ void DMA::Start()
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if ((Cnt & 0x00060000) == 0x00060000)
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CurDstAddr = DstAddr;
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//printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt & 0x04000000)?2:4), (Cnt & 0x04000000)?16:32);
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//printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt&0x04000000)?4:2), (Cnt&0x04000000)?32:16);
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// TODO: NOT MAKE THE DMA INSTANT!!
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if (!(Cnt & 0x04000000))
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@ -89,11 +89,11 @@ void GPU2D::Write16(u32 addr, u16 val)
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{
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case 0x000:
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DispCnt = (DispCnt & 0xFFFF0000) | val;
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printf("[L] DISPCNT=%08X\n", DispCnt);
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//printf("[L] DISPCNT=%08X\n", DispCnt);
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return;
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case 0x002:
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DispCnt = (DispCnt & 0x0000FFFF) | (val << 16);
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printf("[H] DISPCNT=%08X\n", DispCnt);
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//printf("[H] DISPCNT=%08X\n", DispCnt);
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return;
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case 0x008: BGCnt[0] = val; return;
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@ -110,7 +110,7 @@ void GPU2D::Write32(u32 addr, u32 val)
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switch (addr & 0x00000FFF)
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{
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case 0x000:
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printf("DISPCNT=%08X\n", val);
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//printf("DISPCNT=%08X\n", val);
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DispCnt = val;
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return;
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}
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@ -222,7 +222,7 @@ void GPU2D::DrawBG_Text_4bpp(u32 line, u16* dst, u32 bgnum)
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if (Num)
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{
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tileset = (u8*)GPU::VRAM_BBG[((bgcnt & 0x000C) >> 2)];
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tileset = (u8*)GPU::VRAM_BBG[((bgcnt & 0x003C) >> 2)];
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tilemap = (u16*)GPU::VRAM_BBG[((bgcnt & 0x1800) >> 11)];
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tilemap += ((bgcnt & 0x0700) << 2);
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@ -284,6 +284,7 @@ void GPU2D::DrawBG_Text_4bpp(u32 line, u16* dst, u32 bgnum)
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}
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//color = (i >> 4) + ((line >> 4) << 4);
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//if (Num) color = 0;
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//if (yoff>127) color=0;
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if (color)
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dst[i] = curpal[color];
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18
NDS.cpp
18
NDS.cpp
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@ -38,8 +38,10 @@ namespace SPI_Firmware
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namespace NDS
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{
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// TODO: stick all the variables in a big structure?
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// would make it easier to deal with savestates
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// TODO LIST
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// * stick all the variables in a big structure?
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// would make it easier to deal with savestates
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// * move ARM9 TCM to the ARM class (closer to the real thing, and handles "DMA can't access TCM" nicely)
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SchedEvent SchedBuffer[SCHED_BUF_LEN];
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SchedEvent* SchedQueue;
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@ -139,8 +141,8 @@ void LoadROM()
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{
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FILE* f;
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//f = fopen("rom/armwrestler.nds", "rb");
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f = fopen("rom/zorp.nds", "rb");
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f = fopen("rom/armwrestler.nds", "rb");
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//f = fopen("rom/zorp.nds", "rb");
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u32 bootparams[8];
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fseek(f, 0x20, SEEK_SET);
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@ -968,6 +970,13 @@ void ARM9Write8(u32 addr, u8 val)
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void ARM9Write16(u32 addr, u16 val)
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{
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if (addr == ARM9->R[15]) printf("!!!!!!!!!!!!9999 %08X %04X\n", addr, val);
|
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if (addr == 0x02331B44) printf("!! PAL !! %04X %08X\n", val, ARM9->R[15]);
|
||||
/*if (addr >= 0x06218000 && addr < 0x06218000+0x6000 && val)
|
||||
{
|
||||
printf("WRITE TO LAME VRAM %08X %04X %08X, %08X %08X, %08X\n", addr, val, ARM9->R[15], ARM9->R[4], ARM9->R[3],
|
||||
ARM9Read32(ARM9->R[13]+12));
|
||||
//Halt();
|
||||
}*/
|
||||
if (addr < ARM9ITCMSize)
|
||||
{
|
||||
*(u16*)&ARM9ITCM[addr & 0x7FFF] = val;
|
||||
|
|
@ -1026,6 +1035,7 @@ void ARM9Write32(u32 addr, u32 val)
|
|||
{
|
||||
if (addr == ARM9->R[15]) printf("!!!!!!!!!!!!9999 %08X %08X\n", addr, val);
|
||||
if (addr == 0x023549F0) printf("%08X STATE=%08X\n", ARM9->R[15], val);
|
||||
if (addr == 0x02331B44) printf("!! PAL !! %04X %08X %08X\n", val, ARM9->R[15], ARM9Read32(0x23312E8));
|
||||
if (addr < ARM9ITCMSize)
|
||||
{
|
||||
*(u32*)&ARM9ITCM[addr & 0x7FFF] = val;
|
||||
|
|
|
|||
5
main.cpp
5
main.cpp
|
|
@ -35,9 +35,10 @@ LRESULT CALLBACK derpo(HWND window, UINT msg, WPARAM wparam, LPARAM lparam)
|
|||
case WM_CLOSE:
|
||||
printf("close\n");
|
||||
{
|
||||
FILE* f = fopen("vram.bin", "wb");
|
||||
// 6006800 6008000
|
||||
FILE* f = fopen("vramABG.bin", "wb");
|
||||
for (int i = 0; i < 128; i++)
|
||||
fwrite(GPU::VRAM_BBG[i], 16384, 1, f);
|
||||
fwrite(GPU::VRAM_ABG[i], 16384, 1, f);
|
||||
fclose(f);
|
||||
}
|
||||
PostQuitMessage(0);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# depslib dependency file v1.0
|
||||
1484751556 source:c:\documents\sources\melonds\main.cpp
|
||||
1484878707 source:c:\documents\sources\melonds\main.cpp
|
||||
<stdio.h>
|
||||
<windows.h>
|
||||
"NDS.h"
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
|
||||
1481161027 c:\documents\sources\melonds\types.h
|
||||
|
||||
1484868036 source:c:\documents\sources\melonds\nds.cpp
|
||||
1484919120 source:c:\documents\sources\melonds\nds.cpp
|
||||
<stdio.h>
|
||||
<string.h>
|
||||
"NDS.h"
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
"RTC.h"
|
||||
"Wifi.h"
|
||||
|
||||
1484870885 source:c:\documents\sources\melonds\arm.cpp
|
||||
1484917677 source:c:\documents\sources\melonds\arm.cpp
|
||||
<stdio.h>
|
||||
"NDS.h"
|
||||
"ARM.h"
|
||||
|
|
@ -57,7 +57,7 @@
|
|||
|
||||
1481160920 c:\documents\sources\melonds\arminterpreter_alu.h
|
||||
|
||||
1481202027 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
|
||||
1484917510 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
|
||||
<stdio.h>
|
||||
"ARM.h"
|
||||
|
||||
|
|
@ -83,7 +83,7 @@
|
|||
"NDS.h"
|
||||
"SPI.h"
|
||||
|
||||
1484870914 source:c:\documents\sources\melonds\gpu2d.cpp
|
||||
1484920777 source:c:\documents\sources\melonds\gpu2d.cpp
|
||||
<stdio.h>
|
||||
<string.h>
|
||||
"NDS.h"
|
||||
|
|
@ -105,7 +105,7 @@
|
|||
1484612398 c:\documents\sources\melonds\fifo.h
|
||||
"types.h"
|
||||
|
||||
1484762586 source:c:\documents\sources\melonds\dma.cpp
|
||||
1484871851 source:c:\documents\sources\melonds\dma.cpp
|
||||
<stdio.h>
|
||||
"NDS.h"
|
||||
"DMA.h"
|
||||
|
|
|
|||
Loading…
Reference in New Issue