From 7c3108e20f0e8ec5391df2c09bd5af99464f361f Mon Sep 17 00:00:00 2001
From: Jaklyy <102590697+Jaklyy@users.noreply.github.com>
Date: Wed, 5 Jun 2024 14:31:44 -0400
Subject: [PATCH] handle swp instruction aborts

---
 src/ARMInterpreter_LoadStore.cpp | 34 ++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index d28aed0f..c8544a67 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -382,13 +382,16 @@ void A_SWP(ARM* cpu)
     u32 rm = cpu->R[cpu->CurInstr & 0xF];
 
     u32 val;
-    cpu->DataRead32(base, &val);
-    cpu->R[(cpu->CurInstr >> 12) & 0xF] = ROR(val, 8*(base&0x3));
-
-    u32 numD = cpu->DataCycles;
-    cpu->DataWrite32(base, rm);
-    cpu->DataCycles += numD;
-
+    if (cpu->DataRead32(base, &val))
+    {
+        u32 numD = cpu->DataCycles;
+        if (cpu->DataWrite32(base, rm))
+        {
+            // rd only gets updated if both read and write succeed
+            cpu->R[(cpu->CurInstr >> 12) & 0xF] = ROR(val, 8*(base&0x3));
+        }
+        cpu->DataCycles += numD;
+    }
     cpu->AddCycles_CDI();
 }
 
@@ -397,12 +400,17 @@ void A_SWPB(ARM* cpu)
     u32 base = cpu->R[(cpu->CurInstr >> 16) & 0xF];
     u32 rm = cpu->R[cpu->CurInstr & 0xF] & 0xFF;
 
-    cpu->DataRead8(base, &cpu->R[(cpu->CurInstr >> 12) & 0xF]);
-
-    u32 numD = cpu->DataCycles;
-    cpu->DataWrite8(base, rm);
-    cpu->DataCycles += numD;
-
+    u32 val;
+    if (cpu->DataRead8(base, &val))
+    {
+        u32 numD = cpu->DataCycles;
+        if (cpu->DataWrite8(base, rm))
+        {
+            // rd only gets updated if both read and write succeed
+            cpu->R[(cpu->CurInstr >> 12) & 0xF] = val;
+        }
+        cpu->DataCycles += numD;
+    }
     cpu->AddCycles_CDI();
 }