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melonDS
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Disabled Caches, when JIT is enabled

This commit is contained in:
DesperateProgrammer 2024-01-25 09:05:51 +01:00
parent 71b5c829aa
commit 7b8327d3a4
2 changed files with 101 additions and 62 deletions
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75
src/CP15.cpp
View File

@ -1106,7 +1106,7 @@ u32 ARMv5::CP15Read(u32 id) const
// TCM are handled here.
// TODO: later on, handle PU, and maybe caches
// TODO: later on, handle PU
u32 ARMv5::CodeRead32(u32 addr, bool branch)
{
@ -1126,7 +1126,20 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
}
CodeCycles = RegionCodeCycles;
#if 0
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_ICACHEENABLE)
{
if (IsAddressICachable(addr))
{
ICacheLookup(addr);
return *(u32*)&CurICacheLine[addr & (ICACHE_LINELENGTH - 4)];
}
}
} else
{
if (CodeCycles == 0xFF) // cached memory. hax
{
if (branch || !(addr & 0x1F))
@ -1136,17 +1149,7 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
//return *(u32*)&CurICacheLine[addr & 0x1C];
}
#else
if (CP15Control & CP15_CACHE_CR_ICACHEENABLE)
{
if (IsAddressICachable(addr))
{
ICacheLookup(addr);
return *(u32*)&CurICacheLine[addr & (ICACHE_LINELENGTH - 4)];
}
}
#endif
if (CodeMem.Mem) return *(u32*)&CodeMem.Mem[addr & CodeMem.Mask];
return BusRead32(addr);
@ -1164,7 +1167,10 @@ void ARMv5::DataRead8(u32 addr, u32* val)
DataRegion = addr;
#if 1
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_DCACHEENABLE)
{
if (PU_Map[addr >> 12] & 0x10)
@ -1174,7 +1180,7 @@ void ARMv5::DataRead8(u32 addr, u32* val)
return;
}
}
#endif
}
if (addr < ITCMSize)
{
@ -1204,7 +1210,10 @@ void ARMv5::DataRead16(u32 addr, u32* val)
DataRegion = addr;
#if 1
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_DCACHEENABLE)
{
if (PU_Map[addr >> 12] & 0x10)
@ -1214,7 +1223,7 @@ void ARMv5::DataRead16(u32 addr, u32* val)
return;
}
}
#endif
}
addr &= ~1;
@ -1246,7 +1255,10 @@ void ARMv5::DataRead32(u32 addr, u32* val)
DataRegion = addr;
#if 1
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_DCACHEENABLE)
{
if (PU_Map[addr >> 12] & 0x10)
@ -1256,7 +1268,7 @@ void ARMv5::DataRead32(u32 addr, u32* val)
return;
}
}
#endif
}
addr &= ~3;
@ -1281,7 +1293,10 @@ void ARMv5::DataRead32S(u32 addr, u32* val)
{
addr &= ~3;
#if 1
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_DCACHEENABLE)
{
if (PU_Map[addr >> 12] & 0x10)
@ -1291,7 +1306,7 @@ void ARMv5::DataRead32S(u32 addr, u32* val)
return;
}
}
#endif
}
if (addr < ITCMSize)
{
@ -1318,6 +1333,10 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
return;
}
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_DCACHEENABLE)
{
if (PU_Map[addr >> 12] & 0x10)
@ -1326,6 +1345,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
//DCacheInvalidateByAddr(addr);
}
}
}
DataRegion = addr;
@ -1355,6 +1375,10 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
return;
}
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_DCACHEENABLE)
{
if (PU_Map[addr >> 12] & 0x10)
@ -1363,6 +1387,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
// DCacheInvalidateByAddr(addr);
}
}
}
DataRegion = addr;
@ -1394,6 +1419,10 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
return;
}
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_DCACHEENABLE)
{
if (PU_Map[addr >> 12] & 0x10)
@ -1402,6 +1431,7 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
// DCacheInvalidateByAddr(addr);
}
}
}
DataRegion = addr;
@ -1429,6 +1459,10 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
{
addr &= ~3;
#ifdef JIT_ENABLED
if (!NDS.IsJITEnabled())
#endif
{
if (CP15Control & CP15_CACHE_CR_DCACHEENABLE)
{
if (PU_Map[addr >> 12] & 0x10)
@ -1437,6 +1471,7 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
// DCacheInvalidateByAddr(addr);
}
}
}
if (addr < ITCMSize)
{

4
src/NDS.h
View File

@ -302,6 +302,10 @@ public: // TODO: Encapsulate the rest of these members
melonDS::GPU GPU;
melonDS::AREngine AREngine;
#ifdef JIT_ENABLED
bool IsJITEnabled(){return EnableJIT;};
#endif
const u32 ARM7WRAMSize = 0x10000;
u8* ARM7WRAM;