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improve timings further

This commit is contained in:
Jaklyy 2024-07-13 08:01:39 -04:00
parent 789ef21c70
commit 764ee9ea1a
2 changed files with 17 additions and 16 deletions
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11
src/ARM.h
View File

@ -278,12 +278,13 @@ public:
Cycles += std::max(numC, numI); Cycles += std::max(numC, numI);
} }
void AddCycles_CIL(s32 numI, s32 numL) void AddCycles_CIF(s32 numI, s32 numL)
{ {
// (code||internal)+forced interlock // (code||internal)+forced
// used by S variants of multiply instructions on the ARM9 // used by certain multiply instructions
// seems that instead of adding extra hardware logic to allow for handling the memory stage of the instructions during the execute stage // seems likely that the execute stage occurs 2 cycles before the fetch stage ends....?
// it instead seems to force a two cycle interlock allowing for the interlocked cycle to be executed without any special logic + presumably an extra cycle to set flags // could also be in some way related to interlock and the memory stage
// though that doesn't explain why some non-S variants trigger this
s32 numC = CodeCycles; s32 numC = CodeCycles;
numI += 1; numI += 1;
Cycles += std::max(numC, numI) + numL; Cycles += std::max(numC, numI) + numL;

22
src/ARMInterpreter_ALU.cpp
View File

@ -777,7 +777,7 @@ void A_MUL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIL(1, 2); ((ARMv5*)cpu)->AddCycles_CIF(1, 2);
else else
cpu->AddCycles_CI(1); cpu->AddCycles_CI(1);
} }
@ -812,7 +812,7 @@ void A_MLA(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIL(1, 2); ((ARMv5*)cpu)->AddCycles_CIF(1, 2);
else else
cpu->AddCycles_CI(1); cpu->AddCycles_CI(1);
} }
@ -847,9 +847,9 @@ void A_UMULL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIL(1, 2); ((ARMv5*)cpu)->AddCycles_CIF(1, 3);
else else
cpu->AddCycles_CI(1); ((ARMv5*)cpu)->AddCycles_CIF(1, 1);
} }
else else
{ {
@ -886,9 +886,9 @@ void A_UMLAL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIL(1, 2); ((ARMv5*)cpu)->AddCycles_CIF(1, 3);
else else
cpu->AddCycles_CI(1); ((ARMv5*)cpu)->AddCycles_CIF(1, 1);
} }
else else
{ {
@ -922,9 +922,9 @@ void A_SMULL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIL(1, 2); ((ARMv5*)cpu)->AddCycles_CIF(1, 3);
else else
cpu->AddCycles_CI(1); ((ARMv5*)cpu)->AddCycles_CIF(1, 1);
} }
else else
{ {
@ -961,9 +961,9 @@ void A_SMLAL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIL(1, 2); ((ARMv5*)cpu)->AddCycles_CIF(1, 3);
else else
cpu->AddCycles_CI(1); ((ARMv5*)cpu)->AddCycles_CIF(1, 1);
} }
else else
{ {
@ -1497,7 +1497,7 @@ void T_MUL_REG(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
((ARMv5*)cpu)->AddCycles_CIL(1, 2); // checkme? ((ARMv5*)cpu)->AddCycles_CIF(1, 2);
} }
else else
{ {