should addr writes to the fifo take 1 cycle? probably?
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@ -1297,7 +1297,7 @@ bool ARMv5::DataWrite8(u32 addr, u8 val)
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}
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}
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else
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else
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{
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{
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DataCycles = 1;
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DataCycles = 2;
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WriteBufferWrite(addr, 3, 1);
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WriteBufferWrite(addr, 3, 1);
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WriteBufferWrite(val, 0, MemTimings[addr >> 12][1], addr);
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WriteBufferWrite(val, 0, MemTimings[addr >> 12][1], addr);
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}
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}
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@ -1356,7 +1356,7 @@ bool ARMv5::DataWrite16(u32 addr, u16 val)
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}
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}
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else
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else
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{
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{
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DataCycles = 1;
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DataCycles = 2;
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WriteBufferWrite(addr, 3, 1);
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WriteBufferWrite(addr, 3, 1);
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WriteBufferWrite(val, 1, MemTimings[addr >> 12][1], addr);
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WriteBufferWrite(val, 1, MemTimings[addr >> 12][1], addr);
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}
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}
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@ -1415,7 +1415,7 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
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}
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}
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else
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else
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{
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{
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DataCycles = 1;
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DataCycles = 2;
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WriteBufferWrite(addr, 3, 1);
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WriteBufferWrite(addr, 3, 1);
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WriteBufferWrite(val, 2, MemTimings[addr >> 12][2], addr);
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WriteBufferWrite(val, 2, MemTimings[addr >> 12][2], addr);
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}
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}
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