add NWRAM registers
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b03e81edc8
commit
734c9024d5
118
src/DSi.cpp
118
src/DSi.cpp
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@ -197,6 +197,9 @@ bool LoadNAND()
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// read and apply new-WRAM settings
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MBK[0][8] = 0;
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MBK[1][8] = 0;
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u32 mbk[12];
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fseek(f, 0x380, SEEK_SET);
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fread(mbk, 4, 12, f);
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@ -232,7 +235,10 @@ bool LoadNAND()
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MapNWRAMRange(1, 1, mbk[9]);
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MapNWRAMRange(1, 2, mbk[10]);
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// TODO: MBK9 protect thing
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// TODO: find out why it is 0xFF000000
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mbk[11] &= 0x00FFFF0F;
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MBK[0][8] = mbk[11];
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MBK[1][8] = mbk[11];
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// load binaries
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// TODO: optionally support loading from actual NAND?
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@ -364,6 +370,12 @@ void StopNDMAs(u32 cpu, u32 mode)
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void MapNWRAM_A(u32 num, u8 val)
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{
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if (MBK[0][8] & (1 << num))
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{
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printf("trying to map NWRAM_A %d to %02X, but it is write-protected (%08X)\n", num, val, MBK[0][8]);
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return;
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}
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int mbkn = 0, mbks = 8*num;
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u8 oldval = (MBK[0][mbkn] >> mbks) & 0xFF;
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@ -389,6 +401,12 @@ void MapNWRAM_A(u32 num, u8 val)
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void MapNWRAM_B(u32 num, u8 val)
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{
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if (MBK[0][8] & (1 << (8+num)))
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{
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printf("trying to map NWRAM_B %d to %02X, but it is write-protected (%08X)\n", num, val, MBK[0][8]);
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return;
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}
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int mbkn = 1+(num>>2), mbks = 8*(num&3);
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u8 oldval = (MBK[0][mbkn] >> mbks) & 0xFF;
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@ -418,6 +436,12 @@ void MapNWRAM_B(u32 num, u8 val)
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void MapNWRAM_C(u32 num, u8 val)
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{
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if (MBK[0][8] & (1 << (16+num)))
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{
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printf("trying to map NWRAM_C %d to %02X, but it is write-protected (%08X)\n", num, val, MBK[0][8]);
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return;
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}
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int mbkn = 3+(num>>2), mbks = 8*(num&3);
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u8 oldval = (MBK[0][mbkn] >> mbks) & 0xFF;
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@ -928,10 +952,23 @@ bool ARM7GetMemRegion(u32 addr, bool write, NDS::MemRegion* region)
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case (addr+2): return ((val) >> 16) & 0xFF; \
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case (addr+3): return (val) >> 24;
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#define CASE_READ16_32BIT(addr, val) \
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case (addr): return (val) & 0xFFFF; \
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case (addr+2): return (val) >> 16;
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u8 ARM9IORead8(u32 addr)
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{
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switch (addr)
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{
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CASE_READ8_32BIT(0x04004040, MBK[0][0])
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CASE_READ8_32BIT(0x04004044, MBK[0][1])
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CASE_READ8_32BIT(0x04004048, MBK[0][2])
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CASE_READ8_32BIT(0x0400404C, MBK[0][3])
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CASE_READ8_32BIT(0x04004050, MBK[0][4])
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CASE_READ8_32BIT(0x04004054, MBK[0][5])
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CASE_READ8_32BIT(0x04004058, MBK[0][6])
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CASE_READ8_32BIT(0x0400405C, MBK[0][7])
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CASE_READ8_32BIT(0x04004060, MBK[0][8])
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}
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return NDS::ARM9IORead8(addr);
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@ -942,6 +979,16 @@ u16 ARM9IORead16(u32 addr)
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switch (addr)
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{
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case 0x04004004: return 0; // TODO
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CASE_READ16_32BIT(0x04004040, MBK[0][0])
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CASE_READ16_32BIT(0x04004044, MBK[0][1])
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CASE_READ16_32BIT(0x04004048, MBK[0][2])
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CASE_READ16_32BIT(0x0400404C, MBK[0][3])
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CASE_READ16_32BIT(0x04004050, MBK[0][4])
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CASE_READ16_32BIT(0x04004054, MBK[0][5])
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CASE_READ16_32BIT(0x04004058, MBK[0][6])
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CASE_READ16_32BIT(0x0400405C, MBK[0][7])
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CASE_READ16_32BIT(0x04004060, MBK[0][8])
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}
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return NDS::ARM9IORead16(addr);
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@ -953,6 +1000,16 @@ u32 ARM9IORead32(u32 addr)
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{
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case 0x04004010: return 1; // todo
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case 0x04004040: return MBK[0][0];
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case 0x04004044: return MBK[0][1];
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case 0x04004048: return MBK[0][2];
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case 0x0400404C: return MBK[0][3];
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case 0x04004050: return MBK[0][4];
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case 0x04004054: return MBK[0][5];
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case 0x04004058: return MBK[0][6];
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case 0x0400405C: return MBK[0][7];
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case 0x04004060: return MBK[0][8];
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case 0x04004100: return NDMACnt[0];
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case 0x04004104: return NDMAs[0]->SrcAddr;
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case 0x04004108: return NDMAs[0]->DstAddr;
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@ -991,6 +1048,26 @@ void ARM9IOWrite8(u32 addr, u8 val)
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{
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switch (addr)
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{
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case 0x04004040: MapNWRAM_A(0, val); return;
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case 0x04004041: MapNWRAM_A(1, val); return;
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case 0x04004042: MapNWRAM_A(2, val); return;
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case 0x04004043: MapNWRAM_A(3, val); return;
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case 0x04004044: MapNWRAM_B(0, val); return;
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case 0x04004045: MapNWRAM_B(1, val); return;
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case 0x04004046: MapNWRAM_B(2, val); return;
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case 0x04004047: MapNWRAM_B(3, val); return;
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case 0x04004048: MapNWRAM_B(4, val); return;
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case 0x04004049: MapNWRAM_B(5, val); return;
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case 0x0400404A: MapNWRAM_B(6, val); return;
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case 0x0400404B: MapNWRAM_B(7, val); return;
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case 0x0400404C: MapNWRAM_C(0, val); return;
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case 0x0400404D: MapNWRAM_C(1, val); return;
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case 0x0400404E: MapNWRAM_C(2, val); return;
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case 0x0400404F: MapNWRAM_C(3, val); return;
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case 0x04004050: MapNWRAM_C(4, val); return;
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case 0x04004051: MapNWRAM_C(5, val); return;
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case 0x04004052: MapNWRAM_C(6, val); return;
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case 0x04004053: MapNWRAM_C(7, val); return;
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}
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return NDS::ARM9IOWrite8(addr, val);
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@ -1009,6 +1086,10 @@ void ARM9IOWrite32(u32 addr, u32 val)
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{
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switch (addr)
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{
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case 0x04004054: MapNWRAMRange(0, 0, val); return;
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case 0x04004058: MapNWRAMRange(0, 1, val); return;
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case 0x0400405C: MapNWRAMRange(0, 2, val); return;
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case 0x04004100: NDMACnt[0] = val & 0x800F0000; return;
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case 0x04004104: NDMAs[0]->SrcAddr = val & 0xFFFFFFFC; return;
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case 0x04004108: NDMAs[0]->DstAddr = val & 0xFFFFFFFC; return;
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@ -1051,6 +1132,16 @@ u8 ARM7IORead8(u32 addr)
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case 0x04004000: return 0x01;
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case 0x04004001: return 0x01;
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CASE_READ8_32BIT(0x04004040, MBK[1][0])
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CASE_READ8_32BIT(0x04004044, MBK[1][1])
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CASE_READ8_32BIT(0x04004048, MBK[1][2])
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CASE_READ8_32BIT(0x0400404C, MBK[1][3])
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CASE_READ8_32BIT(0x04004050, MBK[1][4])
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CASE_READ8_32BIT(0x04004054, MBK[1][5])
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CASE_READ8_32BIT(0x04004058, MBK[1][6])
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CASE_READ8_32BIT(0x0400405C, MBK[1][7])
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CASE_READ8_32BIT(0x04004060, MBK[1][8])
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case 0x04004500: return DSi_I2C::ReadData();
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case 0x04004501: printf("read I2C CNT %02X\n", DSi_I2C::Cnt); return DSi_I2C::Cnt;
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@ -1078,6 +1169,16 @@ u16 ARM7IORead16(u32 addr)
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case 0x04004004: return 0x0187;
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case 0x04004006: return 0; // JTAG register
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CASE_READ16_32BIT(0x04004040, MBK[1][0])
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CASE_READ16_32BIT(0x04004044, MBK[1][1])
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CASE_READ16_32BIT(0x04004048, MBK[1][2])
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CASE_READ16_32BIT(0x0400404C, MBK[1][3])
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CASE_READ16_32BIT(0x04004050, MBK[1][4])
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CASE_READ16_32BIT(0x04004054, MBK[1][5])
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CASE_READ16_32BIT(0x04004058, MBK[1][6])
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CASE_READ16_32BIT(0x0400405C, MBK[1][7])
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CASE_READ16_32BIT(0x04004060, MBK[1][8])
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case 0x04004D00: return ConsoleID & 0xFFFF;
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case 0x04004D02: return (ConsoleID >> 16) & 0xFFFF;
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case 0x04004D04: return (ConsoleID >> 32) & 0xFFFF;
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@ -1106,6 +1207,16 @@ u32 ARM7IORead32(u32 addr)
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case 0x04004008: return 0x80000000; // HAX
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case 0x04004040: return MBK[1][0];
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case 0x04004044: return MBK[1][1];
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case 0x04004048: return MBK[1][2];
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case 0x0400404C: return MBK[1][3];
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case 0x04004050: return MBK[1][4];
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case 0x04004054: return MBK[1][5];
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case 0x04004058: return MBK[1][6];
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case 0x0400405C: return MBK[1][7];
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case 0x04004060: return MBK[1][8];
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case 0x04004100: return NDMACnt[1];
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case 0x04004104: return NDMAs[4]->SrcAddr;
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case 0x04004108: return NDMAs[4]->DstAddr;
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@ -1198,6 +1309,11 @@ void ARM7IOWrite32(u32 addr, u32 val)
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case 0x04000218: NDS::IE2 = (val & 0x7FF7); NDS::UpdateIRQ(1); return;
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case 0x0400021C: NDS::IF2 &= ~(val & 0x7FF7); NDS::UpdateIRQ(1); return;
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case 0x04004054: MapNWRAMRange(1, 0, val); return;
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case 0x04004058: MapNWRAMRange(1, 1, val); return;
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case 0x0400405C: MapNWRAMRange(1, 2, val); return;
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case 0x04004060: val &= 0x00FFFF0F; MBK[0][8] = val; MBK[1][8] = val; return;
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case 0x04004100: NDMACnt[1] = val & 0x800F0000; return;
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case 0x04004104: NDMAs[4]->SrcAddr = val & 0xFFFFFFFC; return;
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case 0x04004108: NDMAs[4]->DstAddr = val & 0xFFFFFFFC; return;
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