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Fixed unaligned access to data cache

This commit is contained in:
DesperateProgrammer 2024-01-24 14:53:55 +01:00
parent b23cb819bb
commit 71b5c829aa
1 changed files with 10 additions and 3 deletions
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13
src/CP15.cpp
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@ -507,6 +507,8 @@ void ARMv5::DCacheLookup(u32 addr)
void ARMv5::DCacheWrite32(u32 addr, u32 val) void ARMv5::DCacheWrite32(u32 addr, u32 val)
{ {
addr &= ~3;
u32 tag = (addr & ~(DCACHE_LINELENGTH - 1)) | CACHE_FLAG_VALID; u32 tag = (addr & ~(DCACHE_LINELENGTH - 1)) | CACHE_FLAG_VALID;
u32 id = (addr >> DCACHE_LINELENGTH_LOG2) & (DCACHE_LINESPERSET-1); u32 id = (addr >> DCACHE_LINELENGTH_LOG2) & (DCACHE_LINESPERSET-1);
@ -519,7 +521,7 @@ void ARMv5::DCacheWrite32(u32 addr, u32 val)
*(u32 *)&CurDCacheLine[addr & (ICACHE_LINELENGTH-1)] = val; *(u32 *)&CurDCacheLine[addr & (ICACHE_LINELENGTH-1)] = val;
DataCycles = 1; DataCycles = 1;
//Log(LogLevel::Debug,"DCache hit @ %08x -> %08lx\n", addr, ((u32 *)CurDCacheLine)[(addr & (DCACHE_LINELENGTH-1)) >> 2]); //Log(LogLevel::Debug,"DCache write32 hit @ %08x -> %08lx\n", addr, ((u32 *)CurDCacheLine)[(addr & (DCACHE_LINELENGTH-1)) >> 2]);
return; return;
} }
} }
@ -527,6 +529,8 @@ void ARMv5::DCacheWrite32(u32 addr, u32 val)
void ARMv5::DCacheWrite16(u32 addr, u16 val) void ARMv5::DCacheWrite16(u32 addr, u16 val)
{ {
addr &= ~1;
u32 tag = (addr & ~(DCACHE_LINELENGTH - 1)) | CACHE_FLAG_VALID; u32 tag = (addr & ~(DCACHE_LINELENGTH - 1)) | CACHE_FLAG_VALID;
u32 id = (addr >> DCACHE_LINELENGTH_LOG2) & (DCACHE_LINESPERSET-1); u32 id = (addr >> DCACHE_LINELENGTH_LOG2) & (DCACHE_LINESPERSET-1);
@ -539,7 +543,7 @@ void ARMv5::DCacheWrite16(u32 addr, u16 val)
*(u16 *)&CurDCacheLine[addr & (ICACHE_LINELENGTH-1)] = val; *(u16 *)&CurDCacheLine[addr & (ICACHE_LINELENGTH-1)] = val;
DataCycles = 1; DataCycles = 1;
//Log(LogLevel::Debug,"DCache hit @ %08x -> %08lx\n", addr, ((u32 *)CurDCacheLine)[(addr & (DCACHE_LINELENGTH-1)) >> 2]); //Log(LogLevel::Debug,"DCache write16 hit @ %08x -> %04x\n", addr, ((u16 *)CurDCacheLine)[(addr & (DCACHE_LINELENGTH-1)) >> 2]);
return; return;
} }
} }
@ -559,7 +563,7 @@ void ARMv5::DCacheWrite8(u32 addr, u8 val)
*(u8 *)&CurDCacheLine[addr & (ICACHE_LINELENGTH-1)] = val; *(u8 *)&CurDCacheLine[addr & (ICACHE_LINELENGTH-1)] = val;
DataCycles = 1; DataCycles = 1;
//Log(LogLevel::Debug,"DCache hit @ %08x -> %08lx\n", addr, ((u32 *)CurDCacheLine)[(addr & (DCACHE_LINELENGTH-1)) >> 2]); //Log(LogLevel::Debug,"DCache write hit8 @ %08x -> %02x\n", addr, ((u8 *)CurDCacheLine)[(addr & (DCACHE_LINELENGTH-1)) >> 2]);
return; return;
} }
} }
@ -1153,6 +1157,7 @@ void ARMv5::DataRead8(u32 addr, u32* val)
{ {
if (!(PU_Map[addr>>12] & 0x01)) if (!(PU_Map[addr>>12] & 0x01))
{ {
Log(LogLevel::Debug, "data8 abort @ %08lx\n", addr);
DataAbort(); DataAbort();
return; return;
} }
@ -1192,6 +1197,7 @@ void ARMv5::DataRead16(u32 addr, u32* val)
{ {
if (!(PU_Map[addr>>12] & 0x01)) if (!(PU_Map[addr>>12] & 0x01))
{ {
Log(LogLevel::Debug, "data16 abort @ %08lx\n", addr);
DataAbort(); DataAbort();
return; return;
} }
@ -1233,6 +1239,7 @@ void ARMv5::DataRead32(u32 addr, u32* val)
{ {
if (!(PU_Map[addr>>12] & 0x01)) if (!(PU_Map[addr>>12] & 0x01))
{ {
Log(LogLevel::Debug, "data32 abort @ %08lx\n", addr);
DataAbort(); DataAbort();
return; return;
} }