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Queue ICache Prefetch

This commit is contained in:
Jaklyy 2024-12-08 00:25:44 -05:00
parent b40c6bc41d
commit 68b4d96f0d
2 changed files with 8 additions and 2 deletions
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1
src/ARM.h
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@ -761,6 +761,7 @@ public:
void DWrite32S_2(); void DWrite32S_2();
void DWrite32S_3(); void DWrite32S_3();
void WBCheck_2(); void WBCheck_2();
void ICachePrefetch_2();
void DCacheLookup_2(); void DCacheLookup_2();
void DCacheLookup_3(); void DCacheLookup_3();
void DCClearAddr_2(); void DCClearAddr_2();

9
src/CP15.cpp
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@ -1788,8 +1788,8 @@ void ARMv5::CP15Write(u32 id, u32 val)
// we force a fill by looking up the value from cache // we force a fill by looking up the value from cache
// if it wasn't cached yet, it will be loaded into cache // if it wasn't cached yet, it will be loaded into cache
// low bits are set to 0x1C to trick cache streaming // low bits are set to 0x1C to trick cache streaming
printf("PREFETCH ICACHE\n"); CP15Queue = val;
//ICacheLookup((val & ~0x03) | 0x1C); TODO: REIMPLEMENT WITH DEFERENCE QueueFunction(&ARMv5::ICachePrefetch_2);
return; return;
/*case 0x7E0: /*case 0x7E0:
@ -2117,6 +2117,11 @@ u32 ARMv5::CP15Read(const u32 id) const
Log(LogLevel::Debug, "unknown CP15 read op %04X\n", id); Log(LogLevel::Debug, "unknown CP15 read op %04X\n", id);
return 0; return 0;
} }
void ARMv5::ICachePrefetch_2()
{
u32 val = CP15Queue;
ICacheLookup((val & ~0x03) | 0x1C);
}
void ARMv5::DCClearAddr_2() void ARMv5::DCClearAddr_2()
{ {