reset SD controllers during a soft-reset

This commit is contained in:
Arisotura 2020-06-01 16:32:44 +02:00
parent 77f4663f49
commit 6326ddd172
3 changed files with 9 additions and 10 deletions

View File

@ -182,6 +182,9 @@ void SoftReset()
LoadNAND();
SDMMC->Reset();
SDIO->Reset();
NDS::ARM9->JumpTo(BootAddr[0]);
NDS::ARM7->JumpTo(BootAddr[1]);

View File

@ -525,12 +525,12 @@ void DSi_SDHost::Write(u32 addr, u16 val)
}
return;
case 0x002: PortSelect = (val & 0x040F) | (PortSelect & 0x0300); printf("%s: PORT SELECT %04X (%04X)\n", SD_DESC, val, PortSelect); return;
case 0x002: PortSelect = (val & 0x040F) | (PortSelect & 0x0300); return;
case 0x004: Param = (Param & 0xFFFF0000) | val; return;
case 0x006: Param = (Param & 0x0000FFFF) | (val << 16); return;
case 0x008: StopAction = val & 0x0101; return;
case 0x00A: BlockCount16 = val; BlockCountInternal = val; printf("%s: BLOCK COUNT %d\n", SD_DESC, val); return;
case 0x00A: BlockCount16 = val; BlockCountInternal = val; return;
case 0x01C: IRQStatus &= (val | 0xFFFF0000); return;
case 0x01E: IRQStatus &= ((val << 16) | 0xFFFF); return;
@ -575,7 +575,6 @@ void DSi_SDHost::Write(u32 addr, u16 val)
case 0x0D8:
DataCtl = (val & 0x0022);
DataMode = ((DataCtl >> 1) & 0x1) & ((Data32IRQ >> 1) & 0x1);
printf("%s: data mode %d-bit\n", SD_DESC, DataMode?32:16);
return;
case 0x0E0:
@ -598,7 +597,6 @@ void DSi_SDHost::Write(u32 addr, u16 val)
Data32IRQ = (val & 0x1802) | (Data32IRQ & 0x0300);
if (val & (1<<10)) DataFIFO32->Clear();
DataMode = ((DataCtl >> 1) & 0x1) & ((Data32IRQ >> 1) & 0x1);
printf("%s: data mode %d-bit\n", SD_DESC, DataMode?32:16);
return;
case 0x104: BlockLen32 = val & 0x03FF; return;
case 0x108: BlockCount32 = val; return;
@ -803,7 +801,7 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param)
return;
case 18: // read multiple blocks
printf("READ_MULTIPLE_BLOCKS addr=%08X size=%08X\n", param, BlockSize);
//printf("READ_MULTIPLE_BLOCKS addr=%08X size=%08X\n", param, BlockSize);
RWAddress = param;
if (OCR & (1<<30))
{
@ -818,7 +816,7 @@ void DSi_MMCStorage::SendCMD(u8 cmd, u32 param)
return;
case 25: // write multiple blocks
printf("WRITE_MULTIPLE_BLOCKS addr=%08X size=%08X\n", param, BlockSize);
//printf("WRITE_MULTIPLE_BLOCKS addr=%08X size=%08X\n", param, BlockSize);
RWAddress = param;
if (OCR & (1<<30))
{
@ -846,7 +844,7 @@ void DSi_MMCStorage::SendACMD(u8 cmd, u32 param)
switch (cmd)
{
case 6: // set bus width (TODO?)
printf("SET BUS WIDTH %08X\n", param);
//printf("SET BUS WIDTH %08X\n", param);
Host->SendResponse(CSR, true);
return;

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@ -2834,7 +2834,7 @@ u32 ARM9IORead32(u32 addr)
case 0x04000130: return (KeyInput & 0xFFFF) | (KeyCnt << 16);
case 0x04000180: /*printf("ARM9 read IPCSYNC: %04X\n", IPCSync9);*/ return IPCSync9;
case 0x04000180: return IPCSync9;
case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
case 0x040001A4: return NDSCart::ROMCnt;
@ -3043,7 +3043,6 @@ void ARM9IOWrite16(u32 addr, u16 val)
return;
case 0x04000180:
printf("ARM9 IPCSYNC = %04X\n", val);
IPCSync7 &= 0xFFF0;
IPCSync7 |= ((val & 0x0F00) >> 8);
IPCSync9 &= 0xB0FF;
@ -3633,7 +3632,6 @@ void ARM7IOWrite16(u32 addr, u16 val)
case 0x04000138: RTC::Write(val, false); return;
case 0x04000180:
printf("ARM7 IPCSYNC = %04X\n", val);
IPCSync9 &= 0xFFF0;
IPCSync9 |= ((val & 0x0F00) >> 8);
IPCSync7 &= 0xB0FF;