From 60a819c1ed993aaf1d9ab16386d29f70596935ef Mon Sep 17 00:00:00 2001
From: Jaklyy <102590697+Jaklyy@users.noreply.github.com>
Date: Fri, 8 Nov 2024 01:02:36 -0500
Subject: [PATCH] correct handling of T bit changes w/o pipeline flush on arm9

---
 src/ARMInterpreter.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ARMInterpreter.cpp b/src/ARMInterpreter.cpp
index 82dc6876..ff79597e 100644
--- a/src/ARMInterpreter.cpp
+++ b/src/ARMInterpreter.cpp
@@ -129,7 +129,7 @@ void A_MSR_IMM(ARM* cpu)
 
     if (cpu->CPSR & 0x20) [[unlikely]]
     {
-        if (cpu->Num == 0) cpu->NextInstr[1] &= 0xFFFF; // checkme: probably not the right way to handle this
+        if (cpu->Num == 0) cpu->R[15] += 2; // pc should actually increment by 4 one more time after switching to thumb mode without a pipeline flush, this gets the same effect.
         else
         {
             Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: MSR REG T bit change on ARM7\n");
@@ -199,7 +199,7 @@ void A_MSR_REG(ARM* cpu)
 
     if (cpu->CPSR & 0x20) [[unlikely]]
     {
-        if (cpu->Num == 0) cpu->NextInstr[1] &= 0xFFFF; // checkme: probably not the right way to handle this
+        if (cpu->Num == 0) cpu->R[15] += 2; // pc should actually increment by 4 one more time after switching to thumb mode without a pipeline flush, this gets the same effect.
         else
         {
             Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: MSR REG T bit change on ARM7\n");