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don't use param registers for ReadBanked/WriteBanked 

should fix linux build
This commit is contained in:
RSDuck 2020-04-26 20:47:36 +02:00 committed by RSDuck
parent 6d217e1010
commit 5a3607bc68
3 changed files with 40 additions and 41 deletions
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64
src/ARMJIT_x64/ARMJIT_Compiler.cpp
View File

@ -48,10 +48,10 @@ void Compiler::A_Comp_MRS()
{ {
MOV(32, R(RSCRATCH), R(RCPSR)); MOV(32, R(RSCRATCH), R(RCPSR));
AND(32, R(RSCRATCH), Imm8(0x1F)); AND(32, R(RSCRATCH), Imm8(0x1F));
XOR(32, R(ABI_PARAM3), R(ABI_PARAM3)); XOR(32, R(RSCRATCH3), R(RSCRATCH3));
MOV(32, R(ABI_PARAM2), Imm32(15 - 8)); MOV(32, R(RSCRATCH2), Imm32(15 - 8));
CALL(ReadBanked); CALL(ReadBanked);
MOV(32, rd, R(ABI_PARAM3)); MOV(32, rd, R(RSCRATCH3));
} }
else else
MOV(32, rd, R(RCPSR)); MOV(32, rd, R(RCPSR));
@ -75,28 +75,26 @@ void Compiler::A_Comp_MSR()
{ {
MOV(32, R(RSCRATCH), R(RCPSR)); MOV(32, R(RSCRATCH), R(RCPSR));
AND(32, R(RSCRATCH), Imm8(0x1F)); AND(32, R(RSCRATCH), Imm8(0x1F));
XOR(32, R(ABI_PARAM3), R(ABI_PARAM3)); XOR(32, R(RSCRATCH3), R(RSCRATCH3));
MOV(32, R(ABI_PARAM2), Imm32(15 - 8)); MOV(32, R(RSCRATCH2), Imm32(15 - 8));
CALL(ReadBanked); CALL(ReadBanked);
MOV(32, R(RSCRATCH2), Imm32(0xFFFFFF00)); MOV(32, R(RSCRATCH2), Imm32(mask));
MOV(32, R(RSCRATCH3), Imm32(0xFFFFFFFF)); MOV(32, R(RSCRATCH4), R(RSCRATCH2));
AND(32, R(RSCRATCH4), Imm32(0xFFFFFF00));
MOV(32, R(RSCRATCH), R(RCPSR)); MOV(32, R(RSCRATCH), R(RCPSR));
AND(32, R(RSCRATCH), Imm8(0x1F)); AND(32, R(RSCRATCH), Imm8(0x1F));
CMP(32, R(RSCRATCH), Imm8(0x10)); CMP(32, R(RSCRATCH), Imm8(0x10));
CMOVcc(32, RSCRATCH2, R(RSCRATCH3), CC_NE); CMOVcc(32, RSCRATCH2, R(RSCRATCH4), CC_E);
AND(32, R(RSCRATCH2), Imm32(mask));
MOV(32, R(RSCRATCH), R(RSCRATCH2)); MOV(32, R(RSCRATCH4), R(RSCRATCH2));
NOT(32, R(RSCRATCH)); NOT(32, R(RSCRATCH4));
AND(32, R(ABI_PARAM3), R(RSCRATCH)); AND(32, R(RSCRATCH3), R(RSCRATCH4));
AND(32, R(RSCRATCH2), val); AND(32, R(RSCRATCH2), val);
OR(32, R(ABI_PARAM3), R(RSCRATCH2)); OR(32, R(RSCRATCH3), R(RSCRATCH2));
MOV(32, R(RSCRATCH), R(RCPSR)); MOV(32, R(RSCRATCH2), Imm32(15 - 8));
AND(32, R(RSCRATCH), Imm8(0x1F));
MOV(32, R(ABI_PARAM2), Imm32(15 - 8));
CALL(WriteBanked); CALL(WriteBanked);
} }
else else
@ -219,13 +217,13 @@ Compiler::Compiler()
{ {
// RSCRATCH mode // RSCRATCH mode
// ABI_PARAM2 reg number // RSCRATCH2 reg number
// ABI_PARAM3 value in current mode // RSCRATCH3 value in current mode
// ret - ABI_PARAM3 // ret - RSCRATCH3
ReadBanked = (void*)GetWritableCodePtr(); ReadBanked = (void*)GetWritableCodePtr();
CMP(32, R(RSCRATCH), Imm8(0x11)); CMP(32, R(RSCRATCH), Imm8(0x11));
FixupBranch fiq = J_CC(CC_E); FixupBranch fiq = J_CC(CC_E);
SUB(32, R(ABI_PARAM2), Imm8(13 - 8)); SUB(32, R(RSCRATCH2), Imm8(13 - 8));
FixupBranch notEverything = J_CC(CC_L); FixupBranch notEverything = J_CC(CC_L);
CMP(32, R(RSCRATCH), Imm8(0x12)); CMP(32, R(RSCRATCH), Imm8(0x12));
FixupBranch irq = J_CC(CC_E); FixupBranch irq = J_CC(CC_E);
@ -239,30 +237,30 @@ Compiler::Compiler()
RET(); RET();
SetJumpTarget(fiq); SetJumpTarget(fiq);
MOV(32, R(ABI_PARAM3), MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_FIQ))); MOV(32, R(RSCRATCH3), MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_FIQ)));
RET(); RET();
SetJumpTarget(irq); SetJumpTarget(irq);
MOV(32, R(ABI_PARAM3), MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_IRQ))); MOV(32, R(RSCRATCH3), MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_IRQ)));
RET(); RET();
SetJumpTarget(svc); SetJumpTarget(svc);
MOV(32, R(ABI_PARAM3), MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_SVC))); MOV(32, R(RSCRATCH3), MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_SVC)));
RET(); RET();
SetJumpTarget(abt); SetJumpTarget(abt);
MOV(32, R(ABI_PARAM3), MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_ABT))); MOV(32, R(RSCRATCH3), MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_ABT)));
RET(); RET();
SetJumpTarget(und); SetJumpTarget(und);
MOV(32, R(ABI_PARAM3), MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_UND))); MOV(32, R(RSCRATCH3), MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_UND)));
RET(); RET();
} }
{ {
// RSCRATCH mode // RSCRATCH mode
// ABI_PARAM2 reg n // RSCRATCH2 reg n
// ABI_PARAM3 value // RSCRATCH3 value
// carry flag set if the register isn't banked // carry flag set if the register isn't banked
WriteBanked = (void*)GetWritableCodePtr(); WriteBanked = (void*)GetWritableCodePtr();
CMP(32, R(RSCRATCH), Imm8(0x11)); CMP(32, R(RSCRATCH), Imm8(0x11));
FixupBranch fiq = J_CC(CC_E); FixupBranch fiq = J_CC(CC_E);
SUB(32, R(ABI_PARAM2), Imm8(13 - 8)); SUB(32, R(RSCRATCH2), Imm8(13 - 8));
FixupBranch notEverything = J_CC(CC_L); FixupBranch notEverything = J_CC(CC_L);
CMP(32, R(RSCRATCH), Imm8(0x12)); CMP(32, R(RSCRATCH), Imm8(0x12));
FixupBranch irq = J_CC(CC_E); FixupBranch irq = J_CC(CC_E);
@ -277,23 +275,23 @@ Compiler::Compiler()
RET(); RET();
SetJumpTarget(fiq); SetJumpTarget(fiq);
MOV(32, MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_FIQ)), R(ABI_PARAM3)); MOV(32, MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_FIQ)), R(RSCRATCH3));
CLC(); CLC();
RET(); RET();
SetJumpTarget(irq); SetJumpTarget(irq);
MOV(32, MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_IRQ)), R(ABI_PARAM3)); MOV(32, MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_IRQ)), R(RSCRATCH3));
CLC(); CLC();
RET(); RET();
SetJumpTarget(svc); SetJumpTarget(svc);
MOV(32, MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_SVC)), R(ABI_PARAM3)); MOV(32, MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_SVC)), R(RSCRATCH3));
CLC(); CLC();
RET(); RET();
SetJumpTarget(abt); SetJumpTarget(abt);
MOV(32, MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_ABT)), R(ABI_PARAM3)); MOV(32, MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_ABT)), R(RSCRATCH3));
CLC(); CLC();
RET(); RET();
SetJumpTarget(und); SetJumpTarget(und);
MOV(32, MComplex(RCPU, ABI_PARAM2, SCALE_4, offsetof(ARM, R_UND)), R(ABI_PARAM3)); MOV(32, MComplex(RCPU, RSCRATCH2, SCALE_4, offsetof(ARM, R_UND)), R(RSCRATCH3));
CLC(); CLC();
RET(); RET();
} }

1
src/ARMJIT_x64/ARMJIT_Compiler.h
View File

@ -16,6 +16,7 @@ const Gen::X64Reg RCPSR = Gen::R15;
const Gen::X64Reg RSCRATCH = Gen::EAX; const Gen::X64Reg RSCRATCH = Gen::EAX;
const Gen::X64Reg RSCRATCH2 = Gen::EDX; const Gen::X64Reg RSCRATCH2 = Gen::EDX;
const Gen::X64Reg RSCRATCH3 = Gen::ECX; const Gen::X64Reg RSCRATCH3 = Gen::ECX;
const Gen::X64Reg RSCRATCH4 = Gen::R8;
struct ComplexOperand struct ComplexOperand
{ {

16
src/ARMJIT_x64/ARMJIT_LoadStore.cpp
View File

@ -540,14 +540,14 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc
AND(32, R(RSCRATCH), Imm8(0x1F)); AND(32, R(RSCRATCH), Imm8(0x1F));
firstUserMode = false; firstUserMode = false;
} }
MOV(32, R(ABI_PARAM2), Imm32(reg - 8)); MOV(32, R(RSCRATCH2), Imm32(reg - 8));
POP(ABI_PARAM3); POP(RSCRATCH3);
CALL(WriteBanked); CALL(WriteBanked);
FixupBranch sucessfulWritten = J_CC(CC_NC); FixupBranch sucessfulWritten = J_CC(CC_NC);
if (RegCache.Mapping[reg] != INVALID_REG) if (RegCache.Mapping[reg] != INVALID_REG)
MOV(32, R(RegCache.Mapping[reg]), R(ABI_PARAM3)); MOV(32, R(RegCache.Mapping[reg]), R(RSCRATCH3));
else else
SaveReg(reg, ABI_PARAM3); SaveReg(reg, RSCRATCH3);
SetJumpTarget(sucessfulWritten); SetJumpTarget(sucessfulWritten);
} }
else if (RegCache.Mapping[reg] == INVALID_REG) else if (RegCache.Mapping[reg] == INVALID_REG)
@ -600,12 +600,12 @@ s32 Compiler::Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc
firstUserMode = false; firstUserMode = false;
} }
if (RegCache.Mapping[reg] == INVALID_REG) if (RegCache.Mapping[reg] == INVALID_REG)
LoadReg(reg, ABI_PARAM3); LoadReg(reg, RSCRATCH3);
else else
MOV(32, R(ABI_PARAM3), R(RegCache.Mapping[reg])); MOV(32, R(RSCRATCH3), R(RegCache.Mapping[reg]));
MOV(32, R(ABI_PARAM2), Imm32(reg - 8)); MOV(32, R(RSCRATCH2), Imm32(reg - 8));
CALL(ReadBanked); CALL(ReadBanked);
PUSH(ABI_PARAM3); PUSH(RSCRATCH3);
} }
else if (RegCache.Mapping[reg] == INVALID_REG) else if (RegCache.Mapping[reg] == INVALID_REG)
{ {