Merge branch 'pr/1955' into chemical-x
This commit is contained in:
Jaklyy
commit
53cc0378b1
374
src/ARM.h
374
src/ARM.h
|
|
@ -25,6 +25,7 @@
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#include "types.h"
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#include "MemRegion.h"
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#include "MemConstants.h"
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#include "CP15_Constants.h"
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#ifdef GDBSTUB_ENABLED
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#include "debug/GdbStub.h"
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@ -255,7 +256,7 @@ public:
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void Execute();
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// all code accesses are forced nonseq 32bit
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u32 CodeRead32(u32 addr, bool branch);
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u32 CodeRead32(const u32 addr, const bool branch);
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bool DataRead8(u32 addr, u32* val) override;
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bool DataRead16(u32 addr, u32* val) override;
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|
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@ -300,66 +301,371 @@ public:
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AddCycles_MW(DataCycles);
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}
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void GetCodeMemRegion(u32 addr, MemRegion* region);
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void GetCodeMemRegion(const u32 addr, MemRegion* region);
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/**
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* @brief Resets the state of all CP15 registers and variables
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* to power up state.
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* @par Returns
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* Nothing
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*/
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void CP15Reset();
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/**
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* @brief handles read and write operations to a save-state
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* file.
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* @param [in] file Savestate file
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* @par Returns
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* Nothing
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*/
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void CP15DoSavestate(Savestate* file);
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/**
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* @brief Calculates the internal state from @ref DTCMSettings
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* @par Returns
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* Nothing
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*/
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void UpdateDTCMSetting();
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/**
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* @brief Calculates the internal state from @ref ITCMSettings
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* @par Returns
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* Nothing
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*/
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void UpdateITCMSetting();
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void UpdatePURegion(u32 n);
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void UpdatePURegions(bool update_all);
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/**
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* @brief Calculates the internal state from the
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* region protection bits of a specific region number
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* @details
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* This function updates the PU_####Map array in all
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* parts that are occupied by this region. Updating a single
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* region does not take into account the priority of the
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* regions.
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* @param [in] n index of the region from 0 to @ref CP15_REGION_COUNT - 1
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* @par Returns
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* Nothing
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*/
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void UpdatePURegion(const u32 n);
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/**
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* @brief Calculates the internal state from all region
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* protection bits.
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* @details
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* This function updates the internal state in order from the
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* least to the most priotized regions, so that the
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* priority of the regions match the internal state
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* @par Returns
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* Nothing
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*/
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void UpdatePURegions(const bool update_all);
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u32 RandomLineIndex();
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void ICacheLookup(u32 addr);
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void ICacheInvalidateByAddr(u32 addr);
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/**
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* @brief Perform an instruction cache lookup handle
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* @details
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* A cache lookup is performed, if not disabled in
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* @ref CP15BISTTestStateRegister, a hit will returned the
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* cached data, otherwise it returns the result of an memory
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* access instead.
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* If the cache lookup results in a cachemiss and linefill is
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* not disabled in @ref CP15BISTTestStateRegister, will fill
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* fetch all data to fill the entire cacheline directly
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* from the ITCM or bus
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* @param [in] addr Address of the memory to be retreived from
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* cache. The address is internally aligned to an word boundary
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* @return Value of the word at addr
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*/
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u32 ICacheLookup(const u32 addr);
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/**
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* @brief Check if an address is within a instruction cachable
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* region
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* @details
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* Checks the address by looking up the PU_map flags for
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* the address and returns the status of the instruction
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* cache enable flag
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*
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* @param [in] addr Address. May be unaligned.
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* @retval true If the address points to a region, that is
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* enabled for instruction fetches to be cached.
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*/
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inline bool IsAddressICachable(const u32 addr) const;
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/**
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* @brief Invalidates all instruction cache lines
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* @details
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* Clears the @ref CACHE_FLAG_VALID of each cache line in the
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* instruction cache. All other flags and values are kept.
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* @par Returns
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* Nothing
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*/
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void ICacheInvalidateAll();
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void CP15Write(u32 id, u32 val);
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u32 CP15Read(u32 id) const;
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/**
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* @brief Invalidates the instruction cacheline containing
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* the data of an address.
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* @details
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* Searches the cacheline containing the data of an address, and
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* if found clears the @ref CACHE_FLAG_VALID of this cache line.
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* Nothing is done if the address is not present in the cache.
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* @param [in] addr Memory address of the data in the cache line
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* @par Returns
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* Nothing
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*/
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void ICacheInvalidateByAddr(const u32 addr);
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u32 CP15Control;
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/**
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* @brief Invalidates an instruction cache line
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* @details
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* Clears the @ref CACHE_FLAG_VALID of the cacheline given by
|
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* set and index within the set. Nothing is done if the cache
|
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* line does not exist.
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* @param [in] cacheSet index of the internal cache set from
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* 0 to @ref ICACHE_SETS - 1
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* @param [in] cacheLine index of the line within the cache set
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* from 0 to @ref ICACHE_LINESPERSET - 1
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* @par Returns
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* Nothing
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*/
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void ICacheInvalidateBySetAndWay(const u8 cacheSet, const u8 cacheLine);
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u32 RNGSeed;
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/**
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* @brief Perform an data cache lookup handle
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* @details
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* A cache lookup is performed, if not disabled in
|
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* @ref CP15BISTTestStateRegister, a hit will returned the
|
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* cached data, otherwise it returns the result of an memory
|
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* access instead.
|
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* If the cache lookup results in a cachemiss and linefill is
|
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* not disabled in @ref CP15BISTTestStateRegister, will fill
|
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* fetch all data to fill the entire cacheline directly
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* from the ITCM, DTCM or bus
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* @param [in] addr Address of the memory to be retreived from
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* cache. The address is internally aligned to an word boundary
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* @return Value of the word at addr
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*/
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u32 DCacheLookup(const u32 addr);
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u32 DTCMSetting, ITCMSetting;
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/**
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* @brief Updates a word in the data cache if present
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* @param [in] addr Memory address which is written
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* @param [in] val Word value to be written
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* @retval true, if the data was written into the cache and
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* does not need to be updated until cache is
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* cleaned
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* false, to write through
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*/
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bool DCacheWrite32(const u32 addr, const u32 val);
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/**
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* @brief Updates a word in the data cache if present
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* @param [in] addr Memory address which is written
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* @param [in] val Half-Word value to be written
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* @retval true, if the data was written into the cache and
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* does not need to be updated until cache is
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* cleaned
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* false, to write through
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*/
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bool DCacheWrite16(const u32 addr, const u16 val);
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/**
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* @brief Updates a word in the data cache if present
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* @param [in] addr Memory address which is written
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* @param [in] val Byte value to be written
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* @retval true, if the data was written into the cache and
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* does not need to be updated until cache is
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* cleaned
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* false, to write through
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*/
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bool DCacheWrite8(const u32 addr, const u8 val);
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/**
|
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* @brief Check if an address is within a data cachable region
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* @details
|
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* Checks the address by looking up the PU_map flags for
|
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* the address and returns the status of the data cache enable
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* flag
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*
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* @param [in] addr Address. May be unaligned.
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* @retval true If the address points to a region, that is
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* enabled for instruction fetches to be cached.
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*/
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inline bool IsAddressDCachable(const u32 addr) const;
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/**
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* @brief Invalidates the data cacheline containing the data of
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* an address.
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* @details
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* Searches the cacheline containing the data of an address, and
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* if found clears the @ref CACHE_FLAG_VALID of this cache line.
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* Nothing is done if the address is not present in the cache.
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* @par Returns
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* Nothing
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*/
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void DCacheInvalidateAll();
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/**
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* @brief Invalidates the data cacheline containing the data of
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* an address.
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* @details
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* Searches the cacheline containing the data of an address, and
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* if found clears the @ref CACHE_FLAG_VALID of this cache line.
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* Nothing is done if the address is not present in the cache.
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* @par Returns
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* Nothing
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*/
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void DCacheInvalidateByAddr(const u32 addr);
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/**
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* @brief Invalidates an data cache line
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* @details
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* Clears the @ref CACHE_FLAG_VALID of the cacheline given by
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* set and index within the set. Nothing is done if the cache
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* line does not exist.
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* @param [in] cacheSet index of the internal cache set from
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* 0 to @ref DCACHE_SETS - 1
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* @param [in] cacheLine index of the line within the cache set
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* from 0 to @ref DCACHE_LINESPERSET - 1
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* @par Returns
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* Nothing
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*/
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void DCacheInvalidateBySetAndWay(const u8 cacheSet, const u8 cacheLine);
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/**
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* @brief Cleans the entire data cache
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* @details
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* If write-back is enabled in conjunction with the data cache
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* the dirty flags in tags are set if the corresponding cache
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* line is written to.
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* A clean will write the parts of the cache line back
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* that is marked dirty and adds the required cycles to the
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* @ref DataCyces member.
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* @par Returns
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||||
* Nothing
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*/
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void DCacheClearAll();
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/**
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* @brief Cleans a data cache line
|
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* @details
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* If write-back is enabled in conjunction with the data cache
|
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* the dirty flags in tags are set if the corresponding cache
|
||||
* line is written to.
|
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* A clean will write the parts of the cache line back
|
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* that is marked dirty and adds the required cycles to the
|
||||
* @ref DataCyces member.
|
||||
* @param [in] addr Memory address of the data in the cache line
|
||||
* @par Returns
|
||||
* Nothing
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||||
*/
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void DCacheClearByAddr(const u32 addr);
|
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|
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/**
|
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* @brief Cleans a data cache line
|
||||
* @details
|
||||
* If write-back is enabled in conjunction with the data cache
|
||||
* the dirty flags in tags are set if the corresponding cache
|
||||
* line is written to.
|
||||
* A clean will write the parts of the cache line back
|
||||
* that is marked dirty and adds the required cycles to the
|
||||
* @ref DataCyces member.
|
||||
* @param [in] cacheSet index of the internal cache set from
|
||||
* 0 to @ref DCACHE_SETS - 1
|
||||
* @param [in] cacheLine index of the line within the cache set
|
||||
* from 0 to @ref DCACHE_LINESPERSET - 1
|
||||
* @par Returns
|
||||
* Nothing
|
||||
*/
|
||||
void DCacheClearByASetAndWay(const u8 cacheSet, const u8 cacheLine);
|
||||
|
||||
/**
|
||||
* @brief Handles MCR operations writing to cp15 registers
|
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* @details
|
||||
* This function updates the internal state of the emulator when
|
||||
* a cp15 register is written, or triggers the corresponding action
|
||||
* like flushing caches.
|
||||
*
|
||||
* @param [in] id the operation id to be performed, consisting of
|
||||
* (from lower to higher nibble) opcode2, intermediate register,
|
||||
* register and opcode1. Most write operations just take the first 3
|
||||
* into account.
|
||||
* param [in] val value to be written to the cp15 register
|
||||
* @par Returns
|
||||
* Nothing
|
||||
*/
|
||||
void CP15Write(const u32 id, const u32 val);
|
||||
|
||||
/**
|
||||
* @brief handles MRC operations reading from cp15 registers
|
||||
* @details
|
||||
* This function accumulates the regsiter states from the internal
|
||||
* emulator state. It does not modify the internal state of the
|
||||
* emulator or cp15.
|
||||
* @param [in] id the operation id to be performed, consisting of
|
||||
* (from lower to higher nibble) opcode2, intermediate register,
|
||||
* register and opcode1. Most read operations just take the first 3
|
||||
* into account.
|
||||
* @return Value of the cp15 register
|
||||
*/
|
||||
u32 CP15Read(const u32 id) const;
|
||||
|
||||
u32 CP15Control; //! CP15 Register 1: Control Register
|
||||
|
||||
u32 RNGSeed; //! Global cache line fill seed. Used for pseudo random replacement strategy with the instruction and data cache
|
||||
|
||||
u32 DTCMSetting; //! CP15 Register 9 Intermediate 1 Opcode2 0: Data Tightly-Coupled Memory register
|
||||
u32 ITCMSetting; //! CP15 Register 9 Intermediate 1 Opcode2 1: Instruction Tightly-Coupled Memory register
|
||||
u32 DCacheLockDown; //! CP15 Register 9 Intermediate 0 Opcode2 0: Data Cache Lockdown Register
|
||||
u32 ICacheLockDown; //! CP15 Register 9 Intermediate 0 Opcode2 1: Instruction Cache Lockdown Register
|
||||
u32 CacheDebugRegisterIndex; //! CP15: Cache Debug Index Register
|
||||
u32 CP15TraceProcessId; //! CP15: Trace Process Id Register
|
||||
u32 CP15BISTTestStateRegister; //! CP15: BIST Test State Register
|
||||
|
||||
// for aarch64 JIT they need to go up here
|
||||
// to be addressable by a 12-bit immediate
|
||||
u32 ITCMSize;
|
||||
u32 DTCMBase, DTCMMask;
|
||||
s32 RegionCodeCycles;
|
||||
u32 ITCMSize; //! Internal: Size of the memory ITCM is mapped to. @ref ITCM data repeats every @ref ITCMPhysicalSize withhin
|
||||
u32 DTCMBase; //! Internal: DTCMBase Address. The DTCM can be accessed if the address & ~ @ref DTCMMask is equal to thhis base address
|
||||
u32 DTCMMask; //! Internal: DTCM Address Mask used in conjunction with @ref DTCMBase to check for DTCM access
|
||||
s32 RegionCodeCycles; //! Internal: Cached amount of cycles to fetch instruction from the current code region.
|
||||
|
||||
u8 ITCM[ITCMPhysicalSize];
|
||||
u8* DTCM;
|
||||
u8 ITCM[ITCMPhysicalSize]; //! Content of the ITCM
|
||||
u8* DTCM; //! Content of the DTCM
|
||||
|
||||
u8 ICache[0x2000];
|
||||
u32 ICacheTags[64*4];
|
||||
u8 ICacheCount[64];
|
||||
u8 ICache[ICACHE_SIZE]; //! Instruction Cache Content organized in @ref ICACHE_LINESPERSET times @ref ICACHE_SETS times @ref ICACHE_LINELENGTH bytes
|
||||
u32 ICacheTags[ICACHE_LINESPERSET*ICACHE_SETS]; //! Instruction Cache Tags organized in @ref ICACHE_LINESPERSET times @ref ICACHE_SETS Tags
|
||||
u8 ICacheCount; //! Global instruction line fill counter. Used for round-robin replacement strategy with the instruction cache
|
||||
|
||||
u32 PU_CodeCacheable;
|
||||
u32 PU_DataCacheable;
|
||||
u32 PU_DataCacheWrite;
|
||||
u8 DCache[DCACHE_SIZE]; //! Data Cache Content organized in @ref DCACHE_LINESPERSET times @ref DCACHE_SETS times @ref DCACHE_LINELENGTH bytes
|
||||
u32 DCacheTags[DCACHE_LINESPERSET*DCACHE_SETS]; //! Data Cache Tags organized in @ref DCACHE_LINESPERSET times @ref DCACHE_SETS Tags
|
||||
u8 DCacheCount; //! Global data line fill counter. Used for round-robin replacement strategy with the instruction cache
|
||||
|
||||
u32 PU_CodeRW;
|
||||
u32 PU_DataRW;
|
||||
u32 PU_CodeCacheable; //! CP15 Register 2 Opcode2 1: Code Cachable Bits
|
||||
u32 PU_DataCacheable; //! CP15 Register 2 Opcode2 0: Data Cachable Bits
|
||||
u32 PU_DataCacheWrite; //! CP15 Register 3 Opcode2 0: WriteBuffer Control Register
|
||||
|
||||
u32 PU_Region[8];
|
||||
u32 PU_CodeRW; //! CP15 Register 5 Opcode2 3: Code Access Permission register
|
||||
u32 PU_DataRW; //! CP15 Register 5 Opcode2 2: Data Access Permission register
|
||||
|
||||
u32 PU_Region[CP15_REGION_COUNT]; //! CP15 Register 6 Opcode2 0..7: Protection Region Base and Size Register
|
||||
|
||||
// 0=dataR 1=dataW 2=codeR 4=datacache 5=datawrite 6=codecache
|
||||
u8 PU_PrivMap[0x100000];
|
||||
u8 PU_UserMap[0x100000];
|
||||
|
||||
// games operate under system mode, generally
|
||||
//#define PU_Map PU_PrivMap
|
||||
u8* PU_Map;
|
||||
u8 PU_PrivMap[CP15_MAP_ENTRYCOUNT]; /**
|
||||
* Memory mapping flags for Privileged Modes
|
||||
* Bits:
|
||||
* 0 - CP15_MAP_READABLE
|
||||
* 1 - CP15_MAP_WRITEABLE
|
||||
* 2 - CP15_MAP_EXECUTABLE
|
||||
* 4 - CP15_MAP_DCACHEABLE
|
||||
* 5 - CP15_MAP_DCACHEWRITEBACK
|
||||
* 6 - CP15_MAP_ICACHEABLE
|
||||
*/
|
||||
u8 PU_UserMap[CP15_MAP_ENTRYCOUNT]; //! Memory mapping flags for User Mode
|
||||
u8* PU_Map; //! Current valid Region Mapping (is either @ref PU_PrivMap or PU_UserMap)
|
||||
|
||||
// code/16N/32N/32S
|
||||
u8 MemTimings[0x100000][4];
|
||||
|
||||
u8* CurICacheLine;
|
||||
u8 MemTimings[CP15_MAP_ENTRYCOUNT][4];
|
||||
|
||||
bool (*GetMemRegion)(u32 addr, bool write, MemRegion* region);
|
||||
|
||||
|
|
|
|||
|
|
@ -219,7 +219,7 @@ void A_MCR(ARM* cpu)
|
|||
return A_UNK(cpu);
|
||||
|
||||
u32 cp = (cpu->CurInstr >> 8) & 0xF;
|
||||
//u32 op = (cpu->CurInstr >> 21) & 0x7;
|
||||
u32 op = (cpu->CurInstr >> 21) & 0x7;
|
||||
u32 cn = (cpu->CurInstr >> 16) & 0xF;
|
||||
u32 cm = cpu->CurInstr & 0xF;
|
||||
u32 cpinfo = (cpu->CurInstr >> 5) & 0x7;
|
||||
|
|
@ -228,7 +228,7 @@ void A_MCR(ARM* cpu)
|
|||
|
||||
if (cpu->Num==0 && cp==15)
|
||||
{
|
||||
((ARMv5*)cpu)->CP15Write((cn<<8)|(cm<<4)|cpinfo, val);
|
||||
((ARMv5*)cpu)->CP15Write((cn<<8)|(cm<<4)|cpinfo|(op<<12), val);
|
||||
}
|
||||
else if (cpu->Num==1 && cp==14)
|
||||
{
|
||||
|
|
@ -236,7 +236,7 @@ void A_MCR(ARM* cpu)
|
|||
}
|
||||
else
|
||||
{
|
||||
Log(LogLevel::Warn, "bad MCR opcode p%d,%d,%d,%d on ARM%d\n", cp, cn, cm, cpinfo, cpu->Num?7:9);
|
||||
Log(LogLevel::Warn, "bad MCR opcode p%d, %d, reg, c%d, c%d, %d on ARM%d\n", cp, op, cn, cm, cpinfo, cpu->Num?7:9);
|
||||
return A_UNK(cpu); // TODO: check what kind of exception it really is
|
||||
}
|
||||
|
||||
|
|
@ -249,14 +249,14 @@ void A_MRC(ARM* cpu)
|
|||
return A_UNK(cpu);
|
||||
|
||||
u32 cp = (cpu->CurInstr >> 8) & 0xF;
|
||||
//u32 op = (cpu->CurInstr >> 21) & 0x7;
|
||||
u32 op = (cpu->CurInstr >> 21) & 0x7;
|
||||
u32 cn = (cpu->CurInstr >> 16) & 0xF;
|
||||
u32 cm = cpu->CurInstr & 0xF;
|
||||
u32 cpinfo = (cpu->CurInstr >> 5) & 0x7;
|
||||
|
||||
if (cpu->Num==0 && cp==15)
|
||||
{
|
||||
cpu->R[(cpu->CurInstr>>12)&0xF] = ((ARMv5*)cpu)->CP15Read((cn<<8)|(cm<<4)|cpinfo);
|
||||
cpu->R[(cpu->CurInstr>>12)&0xF] = ((ARMv5*)cpu)->CP15Read((cn<<8)|(cm<<4)|cpinfo|(op<<12));
|
||||
}
|
||||
else if (cpu->Num==1 && cp==14)
|
||||
{
|
||||
|
|
@ -264,7 +264,7 @@ void A_MRC(ARM* cpu)
|
|||
}
|
||||
else
|
||||
{
|
||||
Log(LogLevel::Warn, "bad MRC opcode p%d,%d,%d,%d on ARM%d\n", cp, cn, cm, cpinfo, cpu->Num?7:9);
|
||||
Log(LogLevel::Warn, "bad MRC opcode p%d, %d, reg, c%d, c%d, %d on ARM%d\n", cp, op, cn, cm, cpinfo, cpu->Num?7:9);
|
||||
return A_UNK(cpu); // TODO: check what kind of exception it really is
|
||||
}
|
||||
|
||||
|
|
|
|||
1424
src/CP15.cpp
1424
src/CP15.cpp
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
Copyright 2016-2023 melonDS team
|
||||
|
||||
This file is part of melonDS.
|
||||
|
||||
melonDS is free software: you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation, either version 3 of the License, or (at your option)
|
||||
any later version.
|
||||
|
||||
melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with melonDS. If not, see http://www.gnu.org/licenses/.
|
||||
*/
|
||||
|
||||
#ifndef MELONDS_CP15CONSTANTS_H
|
||||
#define MELONDS_CP15CONSTANTS_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
namespace melonDS
|
||||
{
|
||||
|
||||
/* ICACHE Layout constants */
|
||||
constexpr u32 ICACHE_SIZE_LOG2 = 13;
|
||||
constexpr u32 ICACHE_SIZE = 1 << ICACHE_SIZE_LOG2;
|
||||
constexpr u32 ICACHE_SETS_LOG2 = 2;
|
||||
constexpr u32 ICACHE_SETS = 1 << ICACHE_SETS_LOG2;
|
||||
constexpr u32 ICACHE_LINELENGTH_ENCODED = 2;
|
||||
constexpr u32 ICACHE_LINELENGTH_LOG2 = ICACHE_LINELENGTH_ENCODED + 3;
|
||||
constexpr u32 ICACHE_LINELENGTH = 8 * (1 << ICACHE_LINELENGTH_ENCODED);
|
||||
constexpr u32 ICACHE_LINESPERSET = ICACHE_SIZE / (ICACHE_SETS * ICACHE_LINELENGTH);
|
||||
|
||||
/* DCACHE Layout constants */
|
||||
constexpr u32 DCACHE_SIZE_LOG2 = 12;
|
||||
constexpr u32 DCACHE_SIZE = 1 << DCACHE_SIZE_LOG2;
|
||||
constexpr u32 DCACHE_SETS_LOG2 = 2;
|
||||
constexpr u32 DCACHE_SETS = 1 << DCACHE_SETS_LOG2;
|
||||
constexpr u32 DCACHE_LINELENGTH_ENCODED = 2;
|
||||
constexpr u32 DCACHE_LINELENGTH_LOG2 = DCACHE_LINELENGTH_ENCODED + 3;
|
||||
constexpr u32 DCACHE_LINELENGTH = 8 * (1 << DCACHE_LINELENGTH_ENCODED);
|
||||
constexpr u32 DCACHE_LINESPERSET = DCACHE_SIZE / (DCACHE_SETS * DCACHE_LINELENGTH);
|
||||
|
||||
/* CP15 Cache Data TAGs */
|
||||
constexpr u32 CACHE_FLAG_VALID = (1 << 4);
|
||||
constexpr u32 CACHE_FLAG_DIRTY_LOWERHALF = (1 << 2);
|
||||
constexpr u32 CACHE_FLAG_DIRTY_UPPERHALF = (1 << 3);
|
||||
constexpr u32 CACHE_FLAG_DIRTY_MASK = (3 << 2);
|
||||
constexpr u32 CACHE_FLAG_SET_MASK = (3 << 0);
|
||||
constexpr u32 CACHE_FLAG_MASK = 0x1F;
|
||||
|
||||
/* CP15 Cache Type Register */
|
||||
constexpr u32 CACHE_TR_LOCKDOWN_TYPE_B = (7 << 25);
|
||||
constexpr u32 CACHE_TR_NONUNIFIED = (1 << 24);
|
||||
|
||||
/* CP15 I/DCache LockDown registers */
|
||||
constexpr u32 CACHE_LOCKUP_L = (1 << 31);
|
||||
|
||||
/* CP15 Main ID register */
|
||||
constexpr u32 CP15_MAINID_IMPLEMENTOR_ARM = (0x41 << 24);
|
||||
constexpr u32 CP15_MAINID_IMPLEMENTOR_DEC = (0x44 << 24);
|
||||
constexpr u32 CP15_MAINID_IMPLEMENTOR_MOTOROLA = (0x4D << 24);
|
||||
constexpr u32 CP15_MAINID_IMPLEMENTOR_MARVELL = (0x56 << 24);
|
||||
constexpr u32 CP15_MAINID_IMPLEMENTOR_INTEL = (0x69 << 24);
|
||||
constexpr u32 CP15_MAINID_VARIANT_0 = (0 << 20);
|
||||
constexpr u32 CP15_MAINID_ARCH_v4 = (1 << 16);
|
||||
constexpr u32 CP15_MAINID_ARCH_v4T = (2 << 16);
|
||||
constexpr u32 CP15_MAINID_ARCH_v5 = (3 << 16);
|
||||
constexpr u32 CP15_MAINID_ARCH_v5T = (4 << 16);
|
||||
constexpr u32 CP15_MAINID_ARCH_v5TE = (5 << 16);
|
||||
constexpr u32 CP15_MAINID_ARCH_v5TEJ = (6 << 16);
|
||||
constexpr u32 CP15_MAINID_ARCH_v6 = (7 << 16);
|
||||
constexpr u32 CP15_MAINID_IMPLEMENTATION_946 = (0x946 << 4);
|
||||
constexpr u32 CP15_MAINID_REVISION_0 = (0 << 0);
|
||||
constexpr u32 CP15_MAINID_REVISION_1 = (1 << 0);
|
||||
|
||||
/* CP15 TCM Size Register */
|
||||
constexpr u32 CP15_TCMSIZE_DTCM_16KB = (5 << 18);
|
||||
constexpr u32 CP15_TCMSIZE_ITCM_32KB = (6 << 6);
|
||||
|
||||
/* CP15 Cache and Write Buffer Conrol Register */
|
||||
constexpr u32 CP15_CACHE_CR_ROUNDROBIN = (1 << 14);
|
||||
constexpr u32 CP15_CACHE_CR_ICACHEENABLE = (1 << 12);
|
||||
constexpr u32 CP15_CACHE_CR_DCACHEENABLE = (1 << 2);
|
||||
constexpr u32 CP15_CACHE_CR_WRITEBUFFERENABLE = (1 << 3);
|
||||
|
||||
/* CP15 TCM Control Register */
|
||||
constexpr u32 CP15_TCM_CR_DTCM_ENABLE = (1 << 16);
|
||||
constexpr u32 CP15_TCM_CR_ITCM_ENABLE = (1 << 18);
|
||||
constexpr u32 CP15_TCM_CR_DTCM_LOADMODE = (1 << 17); // TODO
|
||||
constexpr u32 CP15_TCM_CR_ITCM_LOADMODE = (1 << 19); // TODO
|
||||
|
||||
/* CP15 DTCM Settings Register */
|
||||
constexpr u32 CP15_DTCM_SIZE_BASE = 0x200;
|
||||
constexpr u32 CP15_DTCM_SIZE_MASK = 0x3E;
|
||||
constexpr u32 CP15_DTCM_SIZE_POS = 1;
|
||||
constexpr u32 CP15_DTCM_SIZE_MIN = 0b00011;
|
||||
constexpr u32 CP15_DTCM_SIZE_MAX = 0b10111;
|
||||
constexpr u32 CP15_DTCM_BASE_MASK = 0xFFFFF000;
|
||||
|
||||
/* CP15 ITCM Settings Register */
|
||||
constexpr u32 CP15_ITCM_SIZE_BASE = 0x200;
|
||||
constexpr u32 CP15_ITCM_SIZE_MASK = 0x3E;
|
||||
constexpr u32 CP15_ITCM_SIZE_POS = 1;
|
||||
constexpr u32 CP15_ITCM_SIZE_MIN = 0b00011;
|
||||
constexpr u32 CP15_ITCM_SIZE_MAX = 0b10111;
|
||||
constexpr u32 CP15_ITCM_BASE_MASK = 0x00000000;
|
||||
|
||||
/* CP15 Control Register */
|
||||
constexpr u32 CP15_CR_MPUENABLE = (1 << 0);
|
||||
constexpr u32 CP15_CR_BIGENDIAN = (1 << 7);
|
||||
constexpr u32 CP15_CR_HIGHEXCEPTIONBASE = (1 << 13);
|
||||
constexpr u32 CP15_CR_DISABLE_THUMBBIT = (1 << 15);
|
||||
constexpr u32 CP15_CR_CHANGEABLE_MASK = CP15_CR_MPUENABLE | CP15_CR_BIGENDIAN | CP15_CACHE_CR_DCACHEENABLE
|
||||
| CP15_CACHE_CR_ICACHEENABLE | CP15_CR_HIGHEXCEPTIONBASE
|
||||
| CP15_TCM_CR_DTCM_ENABLE | CP15_TCM_CR_ITCM_ENABLE
|
||||
| CP15_TCM_CR_DTCM_LOADMODE | CP15_TCM_CR_ITCM_LOADMODE
|
||||
| CP15_CACHE_CR_ROUNDROBIN | CP15_CR_DISABLE_THUMBBIT;
|
||||
/* Note: ARM946E-S Technical reference manual, Chapter 6.5.2 "You cannot directly enable or disable the write buffer"
|
||||
CP15_CACHE_CR_WRITEBUFFERENABLE is always set on the cp15
|
||||
*/
|
||||
|
||||
/* CP15 Internal Exception base value */
|
||||
constexpr u32 CP15_EXCEPTIONBASE_HIGH = 0xFFFF0000;
|
||||
constexpr u32 CP15_EXCEPTIONBASE_LOW = 0x00000000;
|
||||
|
||||
/* CP15 BIST Test State register */
|
||||
constexpr u32 CP15_BIST_TR_DISABLE_ICACHE_STREAMING = (1 << 11);
|
||||
constexpr u32 CP15_BIST_TR_DISABLE_DCACHE_STREAMING = (1 << 12);
|
||||
constexpr u32 CP15_BIST_TR_DISABLE_ICACHE_LINEFILL = (1 << 9);
|
||||
constexpr u32 CP15_BIST_TR_DISABLE_DCACHE_LINEFILL = (1 << 10);
|
||||
|
||||
/* CP15 Region Base and Size Register */
|
||||
constexpr u32 CP15_REGION_COUNT = 8;
|
||||
constexpr u32 CP15_REGION_ENABLE = (1 << 0);
|
||||
constexpr u32 CP15_REGION_SIZE_MASK = (0x1F << 1);
|
||||
constexpr u32 CP15_REGION_BASE_GRANULARITY_LOG2 = 12;
|
||||
constexpr u32 CP15_REGION_BASE_GRANULARITY = (1 << CP15_REGION_BASE_GRANULARITY_LOG2);
|
||||
constexpr u32 CP15_REGION_BASE_MASK = ~(CP15_REGION_BASE_GRANULARITY_LOG2-1);
|
||||
|
||||
/* CP15 Region access mask registers */
|
||||
constexpr u32 CP15_REGIONACCESS_BITS_PER_REGION = 4;
|
||||
constexpr u32 CP15_REGIONACCESS_REGIONMASK = (1 << CP15_REGIONACCESS_BITS_PER_REGION) - 1;
|
||||
|
||||
/* Flags in the melonDS internal PU_PrivMap and PU_UserMap */
|
||||
constexpr u32 CP15_MAP_NOACCESS = 0x00;
|
||||
constexpr u32 CP15_MAP_READABLE = 0x01;
|
||||
constexpr u32 CP15_MAP_WRITEABLE = 0x02;
|
||||
constexpr u32 CP15_MAP_EXECUTABLE = 0x04;
|
||||
constexpr u32 CP15_MAP_DCACHEABLE = 0x10;
|
||||
constexpr u32 CP15_MAP_DCACHEWRITEBACK = 0x20;
|
||||
constexpr u32 CP15_MAP_ICACHEABLE = 0x40;
|
||||
|
||||
constexpr u32 CP15_MAP_ENTRYSIZE_LOG2 = CP15_REGION_BASE_GRANULARITY_LOG2;
|
||||
constexpr u32 CP15_MAP_ENTRYSIZE = (1 << CP15_MAP_ENTRYSIZE_LOG2);
|
||||
constexpr u32 CP15_MAP_ENTRYCOUNT = 1 << (32 - CP15_MAP_ENTRYSIZE_LOG2);
|
||||
|
||||
/* Internal Timing Constants */
|
||||
constexpr u32 BUSCYCLES_N16 = 0;
|
||||
constexpr u32 BUSCYCLES_S16 = 1;
|
||||
constexpr u32 BUSCYCLES_N32 = 2;
|
||||
constexpr u32 BUSCYCLES_S32 = 3;
|
||||
|
||||
constexpr u32 BUSCYCLES_MAP_GRANULARITY_LOG2 = CP15_REGION_BASE_GRANULARITY_LOG2;
|
||||
}
|
||||
|
||||
#endif // MELONDS_CP15CONSTANTS_H
|
||||
|
|
@ -1736,7 +1736,7 @@ void DSi::ARM9Write32(u32 addr, u32 val)
|
|||
return NDS::ARM9Write32(addr, val);
|
||||
}
|
||||
|
||||
bool DSi::ARM9GetMemRegion(u32 addr, bool write, MemRegion* region)
|
||||
bool DSi::ARM9GetMemRegion(const u32 addr, const bool write, MemRegion* region)
|
||||
{
|
||||
assert(ConsoleType == 1);
|
||||
switch (addr & 0xFF000000)
|
||||
|
|
|
|||
|
|
@ -105,7 +105,7 @@ public:
|
|||
void ARM9Write16(u32 addr, u16 val) override;
|
||||
void ARM9Write32(u32 addr, u32 val) override;
|
||||
|
||||
bool ARM9GetMemRegion(u32 addr, bool write, MemRegion* region) override;
|
||||
bool ARM9GetMemRegion(const u32 addr, const bool write, MemRegion* region) override;
|
||||
|
||||
u8 ARM7Read8(u32 addr) override;
|
||||
u16 ARM7Read16(u32 addr) override;
|
||||
|
|
|
|||
|
|
@ -2233,7 +2233,7 @@ void NDS::ARM9Write32(u32 addr, u32 val)
|
|||
//Log(LogLevel::Warn, "unknown arm9 write32 %08X %08X | %08X\n", addr, val, ARM9.R[15]);
|
||||
}
|
||||
|
||||
bool NDS::ARM9GetMemRegion(u32 addr, bool write, MemRegion* region)
|
||||
bool NDS::ARM9GetMemRegion(const u32 addr, const bool write, MemRegion* region)
|
||||
{
|
||||
switch (addr & 0xFF000000)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -309,6 +309,10 @@ public: // TODO: Encapsulate the rest of these members
|
|||
melonDS::GPU GPU;
|
||||
melonDS::AREngine AREngine;
|
||||
|
||||
#ifdef JIT_ENABLED
|
||||
bool IsJITEnabled(){return EnableJIT;};
|
||||
#endif
|
||||
|
||||
const u32 ARM7WRAMSize = 0x10000;
|
||||
u8* ARM7WRAM;
|
||||
|
||||
|
|
@ -445,7 +449,7 @@ public: // TODO: Encapsulate the rest of these members
|
|||
virtual void ARM9Write16(u32 addr, u16 val);
|
||||
virtual void ARM9Write32(u32 addr, u32 val);
|
||||
|
||||
virtual bool ARM9GetMemRegion(u32 addr, bool write, MemRegion* region);
|
||||
virtual bool ARM9GetMemRegion(const u32 addr, const bool write, MemRegion* region);
|
||||
|
||||
virtual u8 ARM7Read8(u32 addr);
|
||||
virtual u16 ARM7Read16(u32 addr);
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include <stdio.h>
|
||||
#include "types.h"
|
||||
|
||||
#define SAVESTATE_MAJOR 12
|
||||
#define SAVESTATE_MAJOR 13
|
||||
#define SAVESTATE_MINOR 1
|
||||
|
||||
namespace melonDS
|
||||
|
|
|
|||
Loading…
Reference in New Issue