more crap implemented!

ARM.cpp

@@ -53,6 +53,8 @@ void ARM::JumpTo(u32 addr)
 {
     // pipeline shit
 
+    //printf("jump from %08X to %08X\n", R[15] - ((CPSR&0x20)?4:8), addr);
+
     if (addr&1)
     {
         addr &= ~1;

ARMInterpreter_ALU.cpp

@@ -716,6 +716,41 @@ A_IMPLEMENT_ALU_OP(MVN)
 
 
 
+s32 T_LSL_IMM(ARM* cpu)
+{
+    u32 op = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 s = (cpu->CurInstr >> 6) & 0x1F;
+    LSL_IMM_S(op, s);
+    cpu->R[cpu->CurInstr & 0x7] = op;
+    cpu->SetNZ(op & 0x80000000,
+               !op);
+    return C_S(1);
+}
+
+s32 T_LSR_IMM(ARM* cpu)
+{
+    u32 op = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 s = (cpu->CurInstr >> 6) & 0x1F;
+    LSR_IMM_S(op, s);
+    cpu->R[cpu->CurInstr & 0x7] = op;
+    cpu->SetNZ(op & 0x80000000,
+               !op);
+    return C_S(1);
+}
+
+s32 T_ASR_IMM(ARM* cpu)
+{
+    u32 op = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 s = (cpu->CurInstr >> 6) & 0x1F;
+    ASR_IMM_S(op, s);
+    cpu->R[cpu->CurInstr & 0x7] = op;
+    cpu->SetNZ(op & 0x80000000,
+               !op);
+    return C_S(1);
+}
+
+//
+
 s32 T_MOV_IMM(ARM* cpu)
 {
     u32 b = cpu->CurInstr & 0xFF;
@@ -730,10 +765,10 @@ s32 T_CMP_IMM(ARM* cpu)
     u32 a = cpu->R[(cpu->CurInstr >> 8) & 0x7];
     u32 b = cpu->CurInstr & 0xFF;
     u32 res = a - b;
-    cpu->SetNZCV(res & 0x80000000, \
+    cpu->SetNZCV(res & 0x80000000,
-                 !res, \
+                 !res,
-                 CARRY_SUB(a, b), \
+                 CARRY_SUB(a, b),
-                 OVERFLOW_SUB(a, b, res)); \
+                 OVERFLOW_SUB(a, b, res));
     return C_S(1);
 }
 
@@ -743,10 +778,10 @@ s32 T_ADD_IMM(ARM* cpu)
     u32 b = cpu->CurInstr & 0xFF;
     u32 res = a + b;
     cpu->R[(cpu->CurInstr >> 8) & 0x7] = res;
-    cpu->SetNZCV(res & 0x80000000, \
+    cpu->SetNZCV(res & 0x80000000,
-                 !res, \
+                 !res,
-                 CARRY_ADD(a, b), \
+                 CARRY_ADD(a, b),
-                 OVERFLOW_ADD(a, b, res)); \
+                 OVERFLOW_ADD(a, b, res));
     return C_S(1);
 }
 
@@ -756,10 +791,208 @@ s32 T_SUB_IMM(ARM* cpu)
     u32 b = cpu->CurInstr & 0xFF;
     u32 res = a - b;
     cpu->R[(cpu->CurInstr >> 8) & 0x7] = res;
-    cpu->SetNZCV(res & 0x80000000, \
+    cpu->SetNZCV(res & 0x80000000,
-                 !res, \
+                 !res,
-                 CARRY_SUB(a, b), \
+                 CARRY_SUB(a, b),
-                 OVERFLOW_SUB(a, b, res)); \
+                 OVERFLOW_SUB(a, b, res));
+    return C_S(1);
+}
+
+
+s32 T_AND_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = a & b;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZ(res & 0x80000000,
+               !res);
+    return C_S(1);
+}
+
+s32 T_EOR_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = a ^ b;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZ(res & 0x80000000,
+               !res);
+    return C_S(1);
+}
+
+s32 T_LSL_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7] & 0xFF;
+    LSL_REG_S(a, b);
+    cpu->R[cpu->CurInstr & 0x7] = a;
+    cpu->SetNZ(a & 0x80000000,
+               !a);
+    return C_S(1) + C_I(1);
+}
+
+s32 T_LSR_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7] & 0xFF;
+    LSR_REG_S(a, b);
+    cpu->R[cpu->CurInstr & 0x7] = a;
+    cpu->SetNZ(a & 0x80000000,
+               !a);
+    return C_S(1) + C_I(1);
+}
+
+s32 T_ASR_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7] & 0xFF;
+    ASR_REG_S(a, b);
+    cpu->R[cpu->CurInstr & 0x7] = a;
+    cpu->SetNZ(a & 0x80000000,
+               !a);
+    return C_S(1) + C_I(1);
+}
+
+s32 T_ADC_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res_tmp = a + b;
+    u32 carry = (cpu->CPSR&0x20000000 ? 1:0);
+    u32 res = res_tmp + carry;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZCV(res & 0x80000000,
+                 !res,
+                 CARRY_ADD(a, b) | CARRY_ADD(res_tmp, carry),
+                 OVERFLOW_ADD(a, b, res_tmp) | OVERFLOW_ADD(res_tmp, carry, res));
+    return C_S(1);
+}
+
+s32 T_SBC_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res_tmp = a - b;
+    u32 carry = (cpu->CPSR&0x20000000 ? 0:1);
+    u32 res = res_tmp - carry;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZCV(res & 0x80000000,
+                 !res,
+                 CARRY_SUB(a, b) | CARRY_SUB(res_tmp, carry),
+                 OVERFLOW_SUB(a, b, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res));
+    return C_S(1);
+}
+
+s32 T_ROR_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7] & 0xFF;
+    ROR_REG_S(a, b);
+    cpu->R[cpu->CurInstr & 0x7] = a;
+    cpu->SetNZ(a & 0x80000000,
+               !a);
+    return C_S(1) + C_I(1);
+}
+
+s32 T_TST_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = a & b;
+    cpu->SetNZ(res & 0x80000000,
+               !res);
+    return C_S(1);
+}
+
+s32 T_NEG_REG(ARM* cpu)
+{
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = -b;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZ(res & 0x80000000,
+               !res);
+    return C_S(1);
+}
+
+s32 T_CMP_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = a - b;
+    cpu->SetNZCV(res & 0x80000000,
+                 !res,
+                 CARRY_SUB(a, b),
+                 OVERFLOW_SUB(a, b, res));
+    return C_S(1);
+}
+
+s32 T_CMN_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = a + b;
+    cpu->SetNZCV(res & 0x80000000,
+                 !res,
+                 CARRY_ADD(a, b),
+                 OVERFLOW_ADD(a, b, res));
+    return C_S(1);
+}
+
+s32 T_ORR_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = a | b;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZ(res & 0x80000000,
+               !res);
+    return C_S(1);
+}
+
+s32 T_MUL_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = a * b;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZ(res & 0x80000000,
+               !res);
+
+    s32 cycles = C_S(1);
+    if (cpu->Num == 0)
+    {
+        cycles += C_I(3);
+    }
+    else
+    {
+        cpu->SetC(0); // carry flag destroyed, they say. whatever that means...
+        if      (a & 0xFF000000) cycles += C_I(4);
+        else if (a & 0x00FF0000) cycles += C_I(3);
+        else if (a & 0x0000FF00) cycles += C_I(2);
+        else                     cycles += C_I(1);
+    }
+    return cycles;
+}
+
+s32 T_BIC_REG(ARM* cpu)
+{
+    u32 a = cpu->R[cpu->CurInstr & 0x7];
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = a & ~b;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZ(res & 0x80000000,
+               !res);
+    return C_S(1);
+}
+
+s32 T_MVN_REG(ARM* cpu)
+{
+    u32 b = cpu->R[(cpu->CurInstr >> 3) & 0x7];
+    u32 res = ~b;
+    cpu->R[cpu->CurInstr & 0x7] = res;
+    cpu->SetNZ(res & 0x80000000,
+               !res);
     return C_S(1);
 }
 

ARMInterpreter_ALU.h

@@ -56,11 +56,32 @@ A_PROTO_ALU_OP(BIC)
 A_PROTO_ALU_OP(MVN)
 
 
+s32 T_LSL_IMM(ARM* cpu);
+s32 T_LSR_IMM(ARM* cpu);
+s32 T_ASR_IMM(ARM* cpu);
+
 s32 T_MOV_IMM(ARM* cpu);
 s32 T_CMP_IMM(ARM* cpu);
 s32 T_ADD_IMM(ARM* cpu);
 s32 T_SUB_IMM(ARM* cpu);
 
+s32 T_AND_REG(ARM* cpu);
+s32 T_EOR_REG(ARM* cpu);
+s32 T_LSL_REG(ARM* cpu);
+s32 T_LSR_REG(ARM* cpu);
+s32 T_ASR_REG(ARM* cpu);
+s32 T_ADC_REG(ARM* cpu);
+s32 T_SBC_REG(ARM* cpu);
+s32 T_ROR_REG(ARM* cpu);
+s32 T_TST_REG(ARM* cpu);
+s32 T_NEG_REG(ARM* cpu);
+s32 T_CMP_REG(ARM* cpu);
+s32 T_CMN_REG(ARM* cpu);
+s32 T_ORR_REG(ARM* cpu);
+s32 T_MUL_REG(ARM* cpu);
+s32 T_BIC_REG(ARM* cpu);
+s32 T_MVN_REG(ARM* cpu);
+
 }
 
 #endif

ARMInterpreter_Branch.cpp

@@ -85,6 +85,27 @@ s32 T_BLX_REG(ARM* cpu)
     return C_S(2) + C_N(1);
 }
 
+s32 T_BL_LONG_1(ARM* cpu)
+{
+    s32 offset = (s32)((cpu->CurInstr & 0x7FF) << 21) >> 9;
+    cpu->R[14] = cpu->R[15] + offset;
+
+    return C_S(1);
+}
+
+s32 T_BL_LONG_2(ARM* cpu)
+{
+    s32 offset = (cpu->CurInstr & 0x7FF) << 1;
+    u32 pc = cpu->R[14] + offset;
+    cpu->R[14] = (cpu->R[15] - 2) | 1;
+
+    if ((cpu->Num==1) || (cpu->CurInstr & (1<<12)))
+        pc |= 1;
+
+    cpu->JumpTo(pc);
+    return C_S(2) + C_N(1);
+}
+
 
 
 }

ARMInterpreter_Branch.h

@@ -13,6 +13,8 @@ s32 A_BLX_REG(ARM* cpu);
 s32 T_BCOND(ARM* cpu);
 s32 T_BX(ARM* cpu);
 s32 T_BLX_REG(ARM* cpu);
+s32 T_BL_LONG_1(ARM* cpu);
+s32 T_BL_LONG_2(ARM* cpu);
 
 }
 

ARMInterpreter_LoadStore.cpp

@@ -196,13 +196,13 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     cpu->Write16(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
     if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
-    return C_N(2) + cpu->MemWaitstate(3, offset);
+    return C_N(2) + cpu->MemWaitstate(2, offset);
 
 #define A_STRH_POST \
     u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     cpu->Write16(addr, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
     cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
-    return C_N(2) + cpu->MemWaitstate(3, addr);
+    return C_N(2) + cpu->MemWaitstate(2, addr);
 
 // TODO: CHECK LDRD/STRD TIMINGS!!
 
@@ -242,13 +242,13 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     cpu->R[(cpu->CurInstr>>12) & 0xF] = cpu->Read16(offset); \
     if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
-    return C_N(2) + cpu->MemWaitstate(3, offset);
+    return C_N(2) + cpu->MemWaitstate(2, offset);
 
 #define A_LDRH_POST \
     u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     cpu->R[(cpu->CurInstr>>12) & 0xF] = cpu->Read16(addr); \
     cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
-    return C_N(2) + cpu->MemWaitstate(3, addr);
+    return C_N(2) + cpu->MemWaitstate(2, addr);
 
 #define A_LDRSB \
     offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
@@ -266,13 +266,13 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s16)cpu->Read16(offset); \
     if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
-    return C_N(2) + cpu->MemWaitstate(3, offset);
+    return C_N(2) + cpu->MemWaitstate(2, offset);
 
 #define A_LDRSH_POST \
     u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s16)cpu->Read16(addr); \
     cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
-    return C_N(2) + cpu->MemWaitstate(3, addr);
+    return C_N(2) + cpu->MemWaitstate(2, addr);
 
 
 #define A_IMPLEMENT_HD_LDRSTR(x) \
@@ -356,5 +356,93 @@ s32 T_LDRB_REG(ARM* cpu)
 }
 
 
+s32 T_STRH_IMM(ARM* cpu)
+{
+    u32 offset = (cpu->CurInstr >> 5) & 0x3E;
+    offset += cpu->R[(cpu->CurInstr >> 3) & 0x7];
+
+    cpu->Write16(offset, cpu->R[cpu->CurInstr & 0x7]);
+    return C_N(2) + cpu->MemWaitstate(2, offset);
+}
+
+s32 T_LDRH_IMM(ARM* cpu)
+{
+    u32 offset = (cpu->CurInstr >> 5) & 0x3E;
+    offset += cpu->R[(cpu->CurInstr >> 3) & 0x7];
+
+    cpu->R[cpu->CurInstr & 0x7] = cpu->Read16(offset);
+    return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(2, offset);
+}
+
+
+s32 T_PUSH(ARM* cpu)
+{
+    int nregs = 0;
+
+    for (int i = 0; i < 8; i++)
+    {
+        if (cpu->CurInstr & (1<<i))
+            nregs++;
+    }
+
+    if (cpu->CurInstr & (1<<8))
+        nregs++;
+
+    u32 base = cpu->R[13];
+    base -= (nregs<<2);
+    cpu->R[13] = base;
+
+    int cycles = C_N(2);
+
+    for (int i = 0; i < 8; i++)
+    {
+        if (cpu->CurInstr & (1<<i))
+        {
+            cpu->Write32(base, cpu->R[i]);
+            cycles += C_S(1) + cpu->MemWaitstate(3, base);
+            base += 4;
+        }
+    }
+
+    if (cpu->CurInstr & (1<<8))
+    {
+        cpu->Write32(base, cpu->R[14]);
+        cycles += C_S(1) + cpu->MemWaitstate(3, base);
+    }
+
+    return cycles - C_S(1);
+}
+
+s32 T_POP(ARM* cpu)
+{
+    u32 base = cpu->R[13];
+
+    int cycles = C_N(1) + C_I(1);
+
+    for (int i = 0; i < 8; i++)
+    {
+        if (cpu->CurInstr & (1<<i))
+        {
+            cpu->R[i] = cpu->Read32(base);
+            cycles += C_S(1) + cpu->MemWaitstate(3, base);
+            base += 4;
+        }
+    }
+
+    if (cpu->CurInstr & (1<<8))
+    {
+        u32 pc = cpu->Read32(base);
+        if (cpu->Num==1) pc |= 0x1;
+        cpu->JumpTo(pc);
+        cycles += C_S(2) + C_N(1) + cpu->MemWaitstate(3, base);
+        base += 4;
+    }
+
+    cpu->R[13] = base;
+
+    return cycles;
+}
+
+
 }
 

ARMInterpreter_LoadStore.h

@@ -45,6 +45,12 @@ s32 T_STRB_REG(ARM* cpu);
 s32 T_LDR_REG(ARM* cpu);
 s32 T_LDRB_REG(ARM* cpu);
 
+s32 T_STRH_IMM(ARM* cpu);
+s32 T_LDRH_IMM(ARM* cpu);
+
+s32 T_PUSH(ARM* cpu);
+s32 T_POP(ARM* cpu);
+
 }
 
 #endif

ARM_InstrTable.h

@@ -1571,40 +1571,40 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
 INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
 {
     // 0000 0000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSL_IMM, T_LSL_IMM, T_LSL_IMM, T_LSL_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSL_IMM, T_LSL_IMM, T_LSL_IMM, T_LSL_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSL_IMM, T_LSL_IMM, T_LSL_IMM, T_LSL_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSL_IMM, T_LSL_IMM, T_LSL_IMM, T_LSL_IMM,
 
     // 0000 0100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSL_IMM, T_LSL_IMM, T_LSL_IMM, T_LSL_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSL_IMM, T_LSL_IMM, T_LSL_IMM, T_LSL_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSL_IMM, T_LSL_IMM, T_LSL_IMM, T_LSL_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSL_IMM, T_LSL_IMM, T_LSL_IMM, T_LSL_IMM,
 
     // 0000 1000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSR_IMM, T_LSR_IMM, T_LSR_IMM, T_LSR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSR_IMM, T_LSR_IMM, T_LSR_IMM, T_LSR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSR_IMM, T_LSR_IMM, T_LSR_IMM, T_LSR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSR_IMM, T_LSR_IMM, T_LSR_IMM, T_LSR_IMM,
 
     // 0000 1100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSR_IMM, T_LSR_IMM, T_LSR_IMM, T_LSR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSR_IMM, T_LSR_IMM, T_LSR_IMM, T_LSR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSR_IMM, T_LSR_IMM, T_LSR_IMM, T_LSR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LSR_IMM, T_LSR_IMM, T_LSR_IMM, T_LSR_IMM,
 
     // 0001 0000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM,
 
     // 0001 0100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM,
 
     // 0001 1000 00
     T_UNK, T_UNK, T_UNK, T_UNK,
@@ -1669,10 +1669,10 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
 
 
     // 0100 0000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_AND_REG, T_EOR_REG, T_LSL_REG, T_LSR_REG,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ASR_REG, T_ADC_REG, T_SBC_REG, T_ROR_REG,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_TST_REG, T_NEG_REG, T_CMP_REG, T_CMN_REG,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_ORR_REG, T_MUL_REG, T_BIC_REG, T_MVN_REG,
 
     // 0100 0100 00
     T_UNK, T_UNK, T_UNK, T_UNK,
@@ -1767,28 +1767,28 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
 
 
     // 1000 0000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_STRH_IMM, T_STRH_IMM, T_STRH_IMM, T_STRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_STRH_IMM, T_STRH_IMM, T_STRH_IMM, T_STRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_STRH_IMM, T_STRH_IMM, T_STRH_IMM, T_STRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_STRH_IMM, T_STRH_IMM, T_STRH_IMM, T_STRH_IMM,
 
     // 1000 0100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_STRH_IMM, T_STRH_IMM, T_STRH_IMM, T_STRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_STRH_IMM, T_STRH_IMM, T_STRH_IMM, T_STRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_STRH_IMM, T_STRH_IMM, T_STRH_IMM, T_STRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_STRH_IMM, T_STRH_IMM, T_STRH_IMM, T_STRH_IMM,
 
     // 1000 1000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM,
 
     // 1000 1100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM,
 
     // 1001 0000 00
     T_UNK, T_UNK, T_UNK, T_UNK,
@@ -1845,8 +1845,8 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
     T_UNK, T_UNK, T_UNK, T_UNK,
 
     // 1011 0100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_PUSH, T_PUSH, T_PUSH, T_PUSH,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_PUSH, T_PUSH, T_PUSH, T_PUSH,
     T_UNK, T_UNK, T_UNK, T_UNK,
     T_UNK, T_UNK, T_UNK, T_UNK,
 
@@ -1857,8 +1857,8 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
     T_UNK, T_UNK, T_UNK, T_UNK,
 
     // 1011 1100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_POP, T_POP, T_POP, T_POP,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_POP, T_POP, T_POP, T_POP,
     T_UNK, T_UNK, T_UNK, T_UNK,
     T_UNK, T_UNK, T_UNK, T_UNK,
 
@@ -1925,38 +1925,38 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
     T_UNK, T_UNK, T_UNK, T_UNK,
 
     // 1110 1000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
 
     // 1110 1100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
 
     // 1111 0000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1,
 
     // 1111 0100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1, T_BL_LONG_1,
 
     // 1111 1000 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
 
     // 1111 1100 00
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK,
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2,
-    T_UNK, T_UNK, T_UNK, T_UNK
+    T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2
 };

melonDS.depend

@@ -8,12 +8,13 @@
 
 1463409689 c:\documents\sources\melonds\types.h
 
-1480030786 source:c:\documents\sources\melonds\nds.cpp
+1480767942 source:c:\documents\sources\melonds\nds.cpp
 	<stdio.h>
+	<string.h>
 	"NDS.h"
 	"ARM.h"
 
-1480736240 source:c:\documents\sources\melonds\arm.cpp
+1480772238 source:c:\documents\sources\melonds\arm.cpp
 	<stdio.h>
 	"NDS.h"
 	"ARM.h"
@@ -23,7 +24,7 @@
 	"types.h"
 	"NDS.h"
 
-1480735162 c:\documents\sources\melonds\arm_instrtable.h
+1480774506 c:\documents\sources\melonds\arm_instrtable.h
 
 1480725698 c:\documents\sources\melonds\arminterpreter.h
 	"types.h"
@@ -38,19 +39,19 @@
 	"ARMInterpreter_LoadStore.h"
 	"ARM_InstrTable.h"
 
-1480732290 c:\documents\sources\melonds\arminterpreter_branch.h
+1480771569 c:\documents\sources\melonds\arminterpreter_branch.h
 
-1480732453 source:c:\documents\sources\melonds\arminterpreter_branch.cpp
+1480772710 source:c:\documents\sources\melonds\arminterpreter_branch.cpp
 	<stdio.h>
 	"ARM.h"
 
-1480730181 c:\documents\sources\melonds\arminterpreter_alu.h
+1480774402 c:\documents\sources\melonds\arminterpreter_alu.h
 
 1480730662 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
 	"ARM.h"
 
-1480734113 c:\documents\sources\melonds\arminterpreter_loadstore.h
+1480771004 c:\documents\sources\melonds\arminterpreter_loadstore.h
 
-1480734224 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp
+1480770968 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp
 	"ARM.h"