* very shitty implementation of save RAM. requires an existing save file for now.
* refine some SPI code, too. mostly removing a useless function. * support 16bit accesses to DMAxCNT registers.
This commit is contained in:
StapleButter
parent
c3e2f7ad9b
commit
516bc30ee3
91
NDS.cpp
91
NDS.cpp
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@ -1317,6 +1317,8 @@ u8 ARM9IORead8(u32 addr)
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{
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switch (addr)
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{
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case 0x040001A2: return NDSCart::ReadSPIData();
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case 0x04000208: return IME[0];
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case 0x04000240: return GPU::VRAMCNT[0];
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@ -1353,6 +1355,15 @@ u16 ARM9IORead16(u32 addr)
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case 0x04000004: return GPU::DispStat[0];
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case 0x04000006: return GPU::VCount;
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case 0x040000B8: return DMAs[0]->Cnt & 0xFFFF;
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case 0x040000BA: return DMAs[0]->Cnt >> 16;
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case 0x040000C4: return DMAs[1]->Cnt & 0xFFFF;
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case 0x040000C6: return DMAs[1]->Cnt >> 16;
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case 0x040000D0: return DMAs[2]->Cnt & 0xFFFF;
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case 0x040000D2: return DMAs[2]->Cnt >> 16;
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case 0x040000DC: return DMAs[3]->Cnt & 0xFFFF;
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case 0x040000DE: return DMAs[3]->Cnt >> 16;
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case 0x040000E0: return ((u16*)DMA9Fill)[0];
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case 0x040000E2: return ((u16*)DMA9Fill)[1];
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case 0x040000E4: return ((u16*)DMA9Fill)[2];
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@ -1385,6 +1396,7 @@ u16 ARM9IORead16(u32 addr)
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}
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case 0x040001A0: return NDSCart::SPICnt;
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case 0x040001A2: return NDSCart::ReadSPIData();
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case 0x04000204: return ExMemCnt[0];
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case 0x04000208: return IME[0];
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@ -1437,6 +1449,7 @@ u32 ARM9IORead32(u32 addr)
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case 0x04000108: return TimerGetCounter(2) | (Timers[2].Cnt << 16);
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case 0x0400010C: return TimerGetCounter(3) | (Timers[3].Cnt << 16);
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case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
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case 0x040001A4: return NDSCart::ROMCnt;
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case 0x04000208: return IME[0];
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@ -1476,7 +1489,7 @@ u32 ARM9IORead32(u32 addr)
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return IPCFIFO7->Peek();
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case 0x04100010:
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if (!(ExMemCnt[0] & (1<<11))) return NDSCart::ReadData();
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if (!(ExMemCnt[0] & (1<<11))) return NDSCart::ReadROMData();
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return 0;
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}
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@ -1500,17 +1513,18 @@ void ARM9IOWrite8(u32 addr, u8 val)
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case 0x040001A0:
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if (!(ExMemCnt[0] & (1<<11)))
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{
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NDSCart::SPICnt &= 0xFF00;
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NDSCart::SPICnt |= val;
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NDSCart::WriteSPICnt((NDSCart::SPICnt & 0xFF00) | val);
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}
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return;
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case 0x040001A1:
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if (!(ExMemCnt[0] & (1<<11)))
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{
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NDSCart::SPICnt &= 0x00FF;
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NDSCart::SPICnt |= (val << 8);
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NDSCart::WriteSPICnt((NDSCart::SPICnt & 0x00FF) | (val << 8));
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}
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return;
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case 0x040001A2:
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NDSCart::WriteSPIData(val);
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return;
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case 0x040001A8: NDSCart::ROMCommand[0] = val; return;
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case 0x040001A9: NDSCart::ROMCommand[1] = val; return;
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@ -1560,6 +1574,15 @@ void ARM9IOWrite16(u32 addr, u16 val)
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{
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case 0x04000004: GPU::SetDispStat(0, val); return;
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case 0x040000B8: DMAs[0]->WriteCnt((DMAs[0]->Cnt & 0xFFFF0000) | val); return;
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case 0x040000BA: DMAs[0]->WriteCnt((DMAs[0]->Cnt & 0x0000FFFF) | (val << 16)); return;
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case 0x040000C4: DMAs[1]->WriteCnt((DMAs[1]->Cnt & 0xFFFF0000) | val); return;
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case 0x040000C6: DMAs[1]->WriteCnt((DMAs[1]->Cnt & 0x0000FFFF) | (val << 16)); return;
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case 0x040000D0: DMAs[2]->WriteCnt((DMAs[2]->Cnt & 0xFFFF0000) | val); return;
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case 0x040000D2: DMAs[2]->WriteCnt((DMAs[2]->Cnt & 0x0000FFFF) | (val << 16)); return;
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case 0x040000DC: DMAs[3]->WriteCnt((DMAs[3]->Cnt & 0xFFFF0000) | val); return;
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case 0x040000DE: DMAs[3]->WriteCnt((DMAs[3]->Cnt & 0x0000FFFF) | (val << 16)); return;
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case 0x04000100: Timers[0].Reload = val; return;
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case 0x04000102: TimerStart(0, val); return;
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case 0x04000104: Timers[1].Reload = val; return;
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@ -1594,7 +1617,10 @@ void ARM9IOWrite16(u32 addr, u16 val)
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return;
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case 0x040001A0:
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if (!(ExMemCnt[0] & (1<<11))) NDSCart::SPICnt = val;
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if (!(ExMemCnt[0] & (1<<11))) NDSCart::WriteSPICnt(val);
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return;
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case 0x040001A2:
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NDSCart::WriteSPIData(val & 0xFF);
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return;
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case 0x040001B8: ROMSeed0[4] = val & 0x7F; return;
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@ -1709,12 +1735,12 @@ void ARM9IOWrite32(u32 addr, u32 val)
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case 0x040001A0:
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if (!(ExMemCnt[0] & (1<<11)))
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{
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NDSCart::SPICnt = val & 0xFFFF;
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// TODO: SPI shit
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NDSCart::WriteSPICnt(val & 0xFFFF);
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NDSCart::WriteSPIData((val >> 16) & 0xFF);
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}
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return;
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case 0x040001A4:
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if (!(ExMemCnt[0] & (1<<11))) NDSCart::WriteCnt(val);
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if (!(ExMemCnt[0] & (1<<11))) NDSCart::WriteROMCnt(val);
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return;
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case 0x040001B0: *(u32*)&ROMSeed0[0] = val; return;
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@ -1768,6 +1794,8 @@ u8 ARM7IORead8(u32 addr)
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{
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case 0x04000138: return RTC::Read() & 0xFF;
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case 0x040001A2: return NDSCart::ReadSPIData();
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case 0x040001C2: return SPI::ReadData();
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case 0x04000208: return IME[1];
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@ -1795,6 +1823,15 @@ u16 ARM7IORead16(u32 addr)
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case 0x04000004: return GPU::DispStat[1];
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case 0x04000006: return GPU::VCount;
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case 0x040000B8: return DMAs[4]->Cnt & 0xFFFF;
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case 0x040000BA: return DMAs[4]->Cnt >> 16;
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case 0x040000C4: return DMAs[5]->Cnt & 0xFFFF;
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case 0x040000C6: return DMAs[5]->Cnt >> 16;
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case 0x040000D0: return DMAs[6]->Cnt & 0xFFFF;
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case 0x040000D2: return DMAs[6]->Cnt >> 16;
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case 0x040000DC: return DMAs[7]->Cnt & 0xFFFF;
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case 0x040000DE: return DMAs[7]->Cnt >> 16;
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case 0x04000100: return TimerGetCounter(4);
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case 0x04000102: return Timers[4].Cnt;
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case 0x04000104: return TimerGetCounter(5);
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@ -1822,8 +1859,9 @@ u16 ARM7IORead16(u32 addr)
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}
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case 0x040001A0: return NDSCart::SPICnt;
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case 0x040001A2: return NDSCart::ReadSPIData();
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case 0x040001C0: return SPI::ReadCnt();
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case 0x040001C0: return SPI::Cnt;
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case 0x040001C2: return SPI::ReadData();
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case 0x04000204: return ExMemCnt[1];
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@ -1869,10 +1907,11 @@ u32 ARM7IORead32(u32 addr)
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case 0x04000108: return TimerGetCounter(6) | (Timers[6].Cnt << 16);
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case 0x0400010C: return TimerGetCounter(7) | (Timers[7].Cnt << 16);
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case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
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case 0x040001A4: return NDSCart::ROMCnt;
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case 0x040001C0:
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return SPI::ReadCnt() | (SPI::ReadData() << 16);
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return SPI::Cnt | (SPI::ReadData() << 16);
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case 0x04000208: return IME[1];
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case 0x04000210: return IE[1];
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@ -1900,7 +1939,7 @@ u32 ARM7IORead32(u32 addr)
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return IPCFIFO9->Peek();
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case 0x04100010:
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if (ExMemCnt[0] & (1<<11)) return NDSCart::ReadData();
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if (ExMemCnt[0] & (1<<11)) return NDSCart::ReadROMData();
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return 0;
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}
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@ -1923,19 +1962,17 @@ void ARM7IOWrite8(u32 addr, u8 val)
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case 0x040001A0:
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if (ExMemCnt[0] & (1<<11))
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{
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NDSCart::SPICnt &= 0xFF00;
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NDSCart::SPICnt |= val;
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NDSCart::WriteSPICnt((NDSCart::SPICnt & 0xFF00) | val);
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}
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return;
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case 0x040001A1:
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if (ExMemCnt[0] & (1<<11))
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{
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NDSCart::SPICnt &= 0x00FF;
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NDSCart::SPICnt |= (val << 8);
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NDSCart::WriteSPICnt((NDSCart::SPICnt & 0x00FF) | (val << 8));
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}
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return;
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case 0x040001A2:
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printf("CART SPI %02X\n", val);
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NDSCart::WriteSPIData(val);
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return;
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case 0x040001A8: NDSCart::ROMCommand[0] = val; return;
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@ -1980,6 +2017,15 @@ void ARM7IOWrite16(u32 addr, u16 val)
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{
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case 0x04000004: GPU::SetDispStat(1, val); return;
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case 0x040000B8: DMAs[4]->WriteCnt((DMAs[4]->Cnt & 0xFFFF0000) | val); return;
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case 0x040000BA: DMAs[4]->WriteCnt((DMAs[4]->Cnt & 0x0000FFFF) | (val << 16)); return;
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case 0x040000C4: DMAs[5]->WriteCnt((DMAs[5]->Cnt & 0xFFFF0000) | val); return;
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case 0x040000C6: DMAs[5]->WriteCnt((DMAs[5]->Cnt & 0x0000FFFF) | (val << 16)); return;
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case 0x040000D0: DMAs[6]->WriteCnt((DMAs[6]->Cnt & 0xFFFF0000) | val); return;
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case 0x040000D2: DMAs[6]->WriteCnt((DMAs[6]->Cnt & 0x0000FFFF) | (val << 16)); return;
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case 0x040000DC: DMAs[7]->WriteCnt((DMAs[7]->Cnt & 0xFFFF0000) | val); return;
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case 0x040000DE: DMAs[7]->WriteCnt((DMAs[7]->Cnt & 0x0000FFFF) | (val << 16)); return;
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case 0x04000100: Timers[4].Reload = val; return;
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case 0x04000102: TimerStart(4, val); return;
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case 0x04000104: Timers[5].Reload = val; return;
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@ -2018,10 +2064,10 @@ void ARM7IOWrite16(u32 addr, u16 val)
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case 0x040001A0:
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if (ExMemCnt[0] & (1<<11))
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NDSCart::SPICnt = val;
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NDSCart::WriteSPICnt(val);
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return;
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case 0x040001A2:
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printf("CART SPI %04X\n", val);
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NDSCart::WriteSPIData(val & 0xFF);
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return;
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case 0x040001B8: ROMSeed0[12] = val & 0x7F; return;
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@ -2030,7 +2076,6 @@ void ARM7IOWrite16(u32 addr, u16 val)
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case 0x040001C0:
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SPI::WriteCnt(val);
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return;
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case 0x040001C2:
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SPI::WriteData(val & 0xFF);
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return;
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@ -2116,12 +2161,12 @@ void ARM7IOWrite32(u32 addr, u32 val)
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case 0x040001A0:
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if (ExMemCnt[0] & (1<<11))
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{
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NDSCart::SPICnt = val & 0xFFFF;
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// TODO: SPI shit
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NDSCart::WriteSPICnt(val & 0xFFFF);
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NDSCart::WriteSPIData((val >> 16) & 0xFF);
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}
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return;
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case 0x040001A4:
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if (ExMemCnt[0] & (1<<11)) NDSCart::WriteCnt(val);
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if (ExMemCnt[0] & (1<<11)) NDSCart::WriteROMCnt(val);
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return;
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case 0x040001B0: *(u32*)&ROMSeed0[8] = val; return;
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167
NDSCart.cpp
167
NDSCart.cpp
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@ -21,6 +21,142 @@
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#include "NDS.h"
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#include "NDSCart.h"
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namespace NDSCart_SRAM
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{
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u8* SRAM;
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u32 SRAMLength;
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u32 AddrLength;
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u32 Hold;
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u8 CurCmd;
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u32 DataPos;
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u8 Data;
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u8 StatusReg;
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u32 Addr;
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void Init()
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{
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SRAM = NULL;
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}
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void Reset()
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{
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if (SRAM) delete[] SRAM;
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FILE* f = fopen("rom/nsmb.sav", "rb"); // TODO: NOT HARDCODE THE FILENAME!!!
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if (f)
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{
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fseek(f, 0, SEEK_END);
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SRAMLength = (u32)ftell(f);
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SRAM = new u8[SRAMLength];
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fseek(f, 0, SEEK_SET);
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fread(SRAM, SRAMLength, 1, f);
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fclose(f);
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switch (SRAMLength)
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{
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case 8192: AddrLength = 2; break;
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default:
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printf("!! BAD SAVE LENGTH %d\n", SRAMLength);
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AddrLength = 2;
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break;
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}
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}
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else
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{
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// TODO: autodetect save type
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SRAMLength = 0;
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}
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Hold = 0;
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CurCmd = 0;
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Data = 0;
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StatusReg = 0x00;
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}
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u8 Read()
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{
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return Data;
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}
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void Write(u8 val, u32 hold)
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{
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if (!hold)
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{
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Hold = 0;
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}
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if (hold && (!Hold))
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{
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CurCmd = val;
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Hold = 1;
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Data = 0;
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DataPos = 1;
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Addr = 0;
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//printf("save SPI command %02X\n", CurCmd);
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return;
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}
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switch (CurCmd)
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{
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case 0x03: // read
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{
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if (DataPos < AddrLength+1)
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{
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Addr <<= 8;
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Addr |= val;
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Data = 0;
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//if (DataPos == AddrLength) printf("save SPI read %08X\n", Addr);
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}
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else
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{
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if (Addr >= SRAMLength)
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Data = 0;
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else
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Data = SRAM[Addr];
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Addr++;
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}
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DataPos++;
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}
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break;
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case 0x04: // write disable
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StatusReg &= ~(1<<1);
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Data = 0;
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break;
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case 0x05: // read status reg
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Data = StatusReg;
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break;
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case 0x06: // write enable
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StatusReg |= (1<<1);
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Data = 0;
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break;
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case 0x9F: // read JEDEC ID
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Data = 0xFF;
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break;
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default:
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printf("unknown save SPI command %02X\n", CurCmd);
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break;
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}
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}
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}
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namespace NDSCart
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{
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@ -154,6 +290,7 @@ void Key2_Encrypt(u8* data, u32 len)
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void Init()
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{
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NDSCart_SRAM::Init();
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}
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void Reset()
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@ -179,6 +316,8 @@ void Reset()
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CmdEncMode = 0;
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DataEncMode = 0;
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NDSCart_SRAM::Reset();
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}
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@ -293,7 +432,7 @@ void ROMPrepareData(u32 param)
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// NDS::ScheduleEvent((ROMCnt & (1<<27)) ? 8:5, ROMPrepareData, 0);
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}
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void WriteCnt(u32 val)
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void WriteROMCnt(u32 val)
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{
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ROMCnt = val & 0xFF7F7FFF;
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@ -437,7 +576,7 @@ void WriteCnt(u32 val)
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//NDS::ScheduleEvent((ROMCnt & (1<<27)) ? 8:5, ROMPrepareData, 0);
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}
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u32 ReadData()
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u32 ReadROMData()
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{
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/*if (ROMCnt & (1<<23))
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{
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||||
|
|
@ -472,4 +611,28 @@ void DMA(u32 addr)
|
|||
EndTransfer();
|
||||
}
|
||||
|
||||
|
||||
void WriteSPICnt(u16 val)
|
||||
{
|
||||
SPICnt = (SPICnt & 0x0080) | (val & 0xE043);
|
||||
}
|
||||
|
||||
u8 ReadSPIData()
|
||||
{
|
||||
if (!(SPICnt & (1<<15))) return 0;
|
||||
if (!(SPICnt & (1<<13))) return 0;
|
||||
|
||||
return NDSCart_SRAM::Read();
|
||||
}
|
||||
|
||||
void WriteSPIData(u8 val)
|
||||
{
|
||||
if (!(SPICnt & (1<<15))) return;
|
||||
if (!(SPICnt & (1<<13))) return;
|
||||
|
||||
// TODO: take delays into account
|
||||
|
||||
NDSCart_SRAM::Write(val, SPICnt&(1<<6));
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -38,10 +38,14 @@ void Reset();
|
|||
|
||||
void LoadROM(char* path);
|
||||
|
||||
void WriteCnt(u32 val);
|
||||
u32 ReadData();
|
||||
void WriteROMCnt(u32 val);
|
||||
u32 ReadROMData();
|
||||
void DMA(u32 addr);
|
||||
|
||||
void WriteSPICnt(u16 val);
|
||||
u8 ReadSPIData();
|
||||
void WriteSPIData(u8 val);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
27
SPI.cpp
27
SPI.cpp
|
|
@ -270,7 +270,7 @@ void Write(u8 val, u32 hold)
|
|||
namespace SPI
|
||||
{
|
||||
|
||||
u16 CNT;
|
||||
u16 Cnt;
|
||||
|
||||
u32 CurDevice;
|
||||
|
||||
|
|
@ -283,29 +283,24 @@ void Init()
|
|||
|
||||
void Reset()
|
||||
{
|
||||
CNT = 0;
|
||||
Cnt = 0;
|
||||
|
||||
SPI_Firmware::Reset();
|
||||
SPI_Powerman::Reset();
|
||||
}
|
||||
|
||||
|
||||
u16 ReadCnt()
|
||||
{
|
||||
return CNT;
|
||||
}
|
||||
|
||||
void WriteCnt(u16 val)
|
||||
{
|
||||
CNT = val & 0xCF03;
|
||||
Cnt = (Cnt & 0x0080) | (val & 0xCF03);
|
||||
if (val & 0x0400) printf("!! CRAPOED 16BIT SPI MODE\n");
|
||||
}
|
||||
|
||||
u8 ReadData()
|
||||
{
|
||||
if (!(CNT & (1<<15))) return 0;
|
||||
if (!(Cnt & (1<<15))) return 0;
|
||||
|
||||
switch (CNT & 0x0300)
|
||||
switch (Cnt & 0x0300)
|
||||
{
|
||||
case 0x0000: return SPI_Powerman::Read();
|
||||
case 0x0100: return SPI_Firmware::Read();
|
||||
|
|
@ -315,18 +310,18 @@ u8 ReadData()
|
|||
|
||||
void WriteData(u8 val)
|
||||
{
|
||||
if (!(CNT & (1<<15))) return;
|
||||
if (!(Cnt & (1<<15))) return;
|
||||
|
||||
// TODO: take delays into account
|
||||
|
||||
switch (CNT & 0x0300)
|
||||
switch (Cnt & 0x0300)
|
||||
{
|
||||
case 0x0000: SPI_Powerman::Write(val, CNT&(1<<11)); break;
|
||||
case 0x0100: SPI_Firmware::Write(val, CNT&(1<<11)); break;
|
||||
default: printf("SPI to unknown device %04X %02X\n", CNT, val); break;
|
||||
case 0x0000: SPI_Powerman::Write(val, Cnt&(1<<11)); break;
|
||||
case 0x0100: SPI_Firmware::Write(val, Cnt&(1<<11)); break;
|
||||
default: printf("SPI to unknown device %04X %02X\n", Cnt, val); break;
|
||||
}
|
||||
|
||||
if (CNT & (1<<14))
|
||||
if (Cnt & (1<<14))
|
||||
NDS::TriggerIRQ(1, NDS::IRQ_SPI);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
|
||||
1481161027 c:\documents\sources\melonds\types.h
|
||||
|
||||
1485868426 source:c:\documents\sources\melonds\nds.cpp
|
||||
1485879135 source:c:\documents\sources\melonds\nds.cpp
|
||||
<stdio.h>
|
||||
<string.h>
|
||||
"NDS.h"
|
||||
|
|
@ -24,7 +24,7 @@
|
|||
"RTC.h"
|
||||
"Wifi.h"
|
||||
|
||||
1485871611 source:c:\documents\sources\melonds\arm.cpp
|
||||
1485873712 source:c:\documents\sources\melonds\arm.cpp
|
||||
<stdio.h>
|
||||
"NDS.h"
|
||||
"ARM.h"
|
||||
|
|
@ -78,9 +78,9 @@
|
|||
"ARM.h"
|
||||
"CP15.h"
|
||||
|
||||
1480957111 c:\documents\sources\melonds\spi.h
|
||||
1485878592 c:\documents\sources\melonds\spi.h
|
||||
|
||||
1485820057 source:c:\documents\sources\melonds\spi.cpp
|
||||
1485878652 source:c:\documents\sources\melonds\spi.cpp
|
||||
<stdio.h>
|
||||
<string.h>
|
||||
"NDS.h"
|
||||
|
|
@ -134,7 +134,7 @@
|
|||
<string.h>
|
||||
"RTC.h"
|
||||
|
||||
1485112531 c:\documents\sources\melonds\ndscart.h
|
||||
1485878561 c:\documents\sources\melonds\ndscart.h
|
||||
"types.h"
|
||||
|
||||
1485813068 source:c:\documents\sources\melonds\ndscart.cpp
|
||||
|
|
|
|||
Loading…
Reference in New Issue