jit: fix thumb hi reg alu and mcr halt
+ mcr/mrc aren't always, msr_imm is never unk on ARM7
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9d180c7bbc
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4a0f6b3b4b
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@ -174,7 +174,7 @@ CompiledBlock CompileBlock(ARM* cpu)
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instrs[i].Info = ARMInstrInfo::Decode(thumb, cpu->Num, instrs[i].Instr);
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i++;
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} while(!instrs[i - 1].Info.Branches() && i < Config::JIT_MaxBlockSize);
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} while(!instrs[i - 1].Info.EndBlock && i < Config::JIT_MaxBlockSize);
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CompiledBlock block = compiler->CompileBlock(cpu, instrs, i);
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@ -663,7 +663,7 @@ void Compiler::T_Comp_ALU_HiReg()
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switch (op)
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{
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case 0x0: // ADD
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Comp_ArithTriOp(&Compiler::ADD, rdMapped, rdMapped, rs, false, opSymmetric|opRetriveCV);
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Comp_ArithTriOp(&Compiler::ADD, rdMapped, rdMapped, rs, false, opSymmetric);
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break;
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case 0x1: // CMP
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Comp_CmpOp(2, rdMapped, rs, false);
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@ -671,8 +671,6 @@ void Compiler::T_Comp_ALU_HiReg()
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case 0x2: // MOV
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if (rdMapped != rs)
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MOV(32, rdMapped, rs);
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TEST(32, rdMapped, rdMapped);
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Comp_RetriveFlags(false, false, false);
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break;
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}
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@ -235,17 +235,24 @@ void Compiler::T_Comp_B()
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void Compiler::T_Comp_BranchXchangeReg()
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{
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bool link = CurInstr.Instr & (1 << 7);
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if (link && Num == 1)
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if (link)
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{
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if (Num == 1)
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{
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printf("BLX unsupported on ARM7!!!\n");
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return;
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}
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OpArg rn = MapReg(CurInstr.A_Reg(3));
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if (link)
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MOV(32, R(RSCRATCH), MapReg(CurInstr.A_Reg(3)));
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MOV(32, MapReg(14), Imm32(R15 - 1));
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Comp_JumpTo(RSCRATCH);
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}
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else
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{
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OpArg rn = MapReg(CurInstr.A_Reg(3));
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Comp_JumpTo(rn.GetSimpleReg());
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}
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}
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void Compiler::T_Comp_BL_LONG_1()
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{
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@ -152,11 +152,11 @@ const u32 A_BX = A_BranchAlways | A_Read0 | ak(ak_BX);
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const u32 A_BLX_REG = A_BranchAlways | A_Link | A_Read0 | ak(ak_BLX_REG);
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const u32 A_UNK = A_BranchAlways | A_Link | ak(ak_UNK);
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const u32 A_MSR_IMM = A_UnkOnARM7 | ak(ak_MSR_IMM);
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const u32 A_MSR_REG = A_Read0 | A_UnkOnARM7 | ak(ak_MSR_REG);
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const u32 A_MRS = A_Write12 | A_UnkOnARM7 | ak(ak_MRS);
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const u32 A_MCR = A_Read12 | A_UnkOnARM7 | ak(ak_MCR);
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const u32 A_MRC = A_Write12 | A_UnkOnARM7 | ak(ak_MRC);
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const u32 A_MSR_IMM = ak(ak_MSR_IMM);
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const u32 A_MSR_REG = A_Read0 | ak(ak_MSR_REG);
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const u32 A_MRS = A_Write12 | ak(ak_MRS);
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const u32 A_MCR = A_Read12 | ak(ak_MCR);
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const u32 A_MRC = A_Write12 | ak(ak_MRC);
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const u32 A_SVC = A_BranchAlways | A_Link | ak(ak_SVC);
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// THUMB
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@ -310,6 +310,7 @@ Info Decode(bool thumb, u32 num, u32 instr)
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res.DstRegs |= 1 << 15;
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res.Kind = (data >> 16) & 0x3F;
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res.EndBlock = res.Branches();
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return res;
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}
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@ -324,6 +325,26 @@ Info Decode(bool thumb, u32 num, u32 instr)
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res.Kind = (data >> 13) & 0x1FF;
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if (res.Kind == ak_MCR)
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{
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u32 cn = (instr >> 16) & 0xF;
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u32 cm = instr & 0xF;
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u32 cpinfo = (instr >> 5) & 0x7;
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u32 id = (cn<<8)|(cm<<4)|cpinfo;
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if (id == 0x704 || id == 0x782)
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res.EndBlock |= true;
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}
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if (res.Kind == ak_MCR || res.Kind == ak_MRC)
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{
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u32 cp = ((instr >> 8) & 0xF);
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if ((num == 0 && cp != 15) || (num == 1 && cp != 14))
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{
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printf("happens\n");
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data = A_UNK;
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res.Kind = ak_UNK;
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}
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}
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if (data & A_Read0)
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res.SrcRegs |= 1 << (instr & 0xF);
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if (data & A_Read16)
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@ -361,6 +382,8 @@ Info Decode(bool thumb, u32 num, u32 instr)
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if (res.Kind == ak_LDM)
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res.DstRegs |= instr & (1 << 15); // this is right
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res.EndBlock |= res.Branches();
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return res;
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}
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}
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@ -220,6 +220,7 @@ struct Info
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u16 DstRegs, SrcRegs;
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u16 Kind;
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bool EndBlock;
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bool Branches()
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{
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return DstRegs & (1 << 15);
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