From 457dd56b88b060cd981e7cb9a8a24d8fca9efcbf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Valt=C3=BDr=20K=C3=A1ri=20Dan=C3=ADelsson?=
 <valtyrkarid@gmail.com>
Date: Wed, 27 Jul 2022 17:01:31 +0200
Subject: [PATCH] constexpr-s the DMA timing tables (#1489)

---
 src/DMA.h         |  2 +-
 src/DMA_Timings.h | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/DMA.h b/src/DMA.h
index 7866631e..c3d42def 100644
--- a/src/DMA.h
+++ b/src/DMA.h
@@ -96,7 +96,7 @@ private:
     bool IsGXFIFODMA;
 
     u32 MRAMBurstCount;
-    u8* MRAMBurstTable;
+    const u8* MRAMBurstTable;
 };
 
 #endif
diff --git a/src/DMA_Timings.h b/src/DMA_Timings.h
index 1283751b..f25d196d 100644
--- a/src/DMA_Timings.h
+++ b/src/DMA_Timings.h
@@ -43,9 +43,9 @@ namespace DMATiming
 // setting. Timings are such that the nonseq setting only matters for the first
 // access, and minor edge cases (like the last of a 0x20000-byte block).
 
-u8 MRAMDummy[1] = {0};
+constexpr u8 MRAMDummy[1] = {0};
 
-u8 MRAMRead16Bursts[][256] =
+constexpr u8 MRAMRead16Bursts[][256] =
 {
     // main RAM to regular 16bit or 32bit bus (similar)
     {7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
@@ -119,7 +119,7 @@ u8 MRAMRead16Bursts[][256] =
      0},
 };
 
-u8 MRAMRead32Bursts[][256] =
+constexpr u8 MRAMRead32Bursts[][256] =
 {
     // main RAM to regular 16bit bus
     {9, 4, 3, 3, 3, 3, 3, 3, 3, 3,
@@ -178,7 +178,7 @@ u8 MRAMRead32Bursts[][256] =
      0},
 };
 
-u8 MRAMWrite16Bursts[][256] =
+constexpr u8 MRAMWrite16Bursts[][256] =
 {
     // regular 16bit or 32bit bus to main RAM (similar)
     {8, 2, 2, 2, 2, 2, 2, 2, 2, 2,
@@ -209,7 +209,7 @@ u8 MRAMWrite16Bursts[][256] =
      0},
 };
 
-u8 MRAMWrite32Bursts[][256] =
+constexpr u8 MRAMWrite32Bursts[][256] =
 {
     // regular 16bit bus to main RAM
     {9, 4, 4, 4, 4, 4, 4, 4, 4, 4,