actually make the NAND thing work
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2c5049d40a
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@ -1177,7 +1177,12 @@ void CartRetailNAND::Reset()
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{
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SRAMAddr = 0;
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SRAMStatus = 0x20;
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SRAMReadWindow = 0;
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SRAMWindow = 0;
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// ROM header 94/96 = SRAM addr start / 0x20000
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SRAMBase = *(u16*)&ROM[0x96] << 17;
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memset(SRAMWriteBuffer, 0, 0x800);
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}
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void CartRetailNAND::DoSavestate(Savestate* file)
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@ -1210,16 +1215,52 @@ void CartRetailNAND::LoadSave(const char* path, u32 type)
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int CartRetailNAND::ROMCommandStart(u8* cmd, u8* data, u32 len)
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{
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// ROM header 94/96 = save addr start / 0x20000
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switch (cmd[0])
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{
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case 0x85: // write enable?
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SRAMStatus |= (1<<4);
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case 0x81: // write data
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if ((SRAMStatus & (1<<4)) && SRAMWindow >= SRAMBase && SRAMWindow < (SRAMBase+0x800000))
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{
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u32 addr = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
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// the command is issued 4 times, each with the same address
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// seems they use the one from the first command (CHECKME)
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if (!SRAMAddr)
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SRAMAddr = addr;
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}
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else
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SRAMAddr = 0;
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return 1;
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case 0x82: // commit write
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if (SRAMAddr && SRAMWritePos)
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{
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if (SRAMLength && SRAMAddr < (SRAMBase+SRAMLength-0x20000))
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{
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memcpy(&SRAM[SRAMAddr - SRAMBase], SRAMWriteBuffer, 0x800);
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SRAMFileDirty = true;
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}
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SRAMAddr = 0;
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SRAMWritePos = 0;
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}
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SRAMStatus &= ~(1<<4);
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return 0;
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case 0x84: // discard write buffer
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SRAMAddr = 0;
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SRAMWritePos = 0;
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return 0;
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case 0x85: // write enable
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if (SRAMWindow)
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{
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SRAMStatus |= (1<<4);
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SRAMWritePos = 0;
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}
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return 0;
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case 0x8B: // revert to ROM read mode
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SRAMReadWindow = 0;
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SRAMWindow = 0;
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return 0;
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case 0x94: // return ID data
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@ -1249,7 +1290,7 @@ int CartRetailNAND::ROMCommandStart(u8* cmd, u8* data, u32 len)
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// NAND remains stuck 'busy' forever if this is less than the starting SRAM address
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// TODO.
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SRAMReadWindow = addr;
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SRAMWindow = addr;
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}
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return 0;
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@ -1257,8 +1298,9 @@ int CartRetailNAND::ROMCommandStart(u8* cmd, u8* data, u32 len)
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{
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u32 addr = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
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if (SRAMReadWindow == 0)
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if (SRAMWindow == 0)
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{
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// regular ROM mode
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memset(data, 0, len);
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if (((addr + len - 1) >> 12) != (addr >> 12))
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@ -1272,21 +1314,13 @@ int CartRetailNAND::ROMCommandStart(u8* cmd, u8* data, u32 len)
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}
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else
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{
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// SRAM mode
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memset(data, 0xFF, len);
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u32 sramstart = *(u16*)&ROM[0x96] << 17;
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u32 sramend = sramstart + 0x800000; // CHECKME
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if (SRAMReadWindow >= sramstart && SRAMReadWindow < sramend &&
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addr >= SRAMReadWindow && addr < (SRAMReadWindow+0x20000))
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if (SRAMWindow >= SRAMBase && SRAMWindow < (SRAMBase+SRAMLength) &&
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addr >= SRAMWindow && addr < (SRAMWindow+0x20000))
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{
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// TODO!!
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if (addr == (sramstart+0x7FF800))
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{
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u8 iddata[0x10] = {0xEC, 0x00, 0x9E, 0xA1, 0x51, 0x65, 0x34, 0x35, 0x30, 0x35, 0x30, 0x31, 0x19, 0x19, 0x02, 0x0A};
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memcpy(data, iddata, std::min(len, 0x10u));
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printf("READING ID BLOCK @ %08X\n", addr);
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}
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memcpy(data, &SRAM[addr - SRAMBase], len);
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}
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}
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}
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@ -1297,17 +1331,13 @@ int CartRetailNAND::ROMCommandStart(u8* cmd, u8* data, u32 len)
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// status bits
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// bit5: ready
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// bit4: write enable
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printf("NAND STATUS %02X\n", SRAMStatus);
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for (u32 i = 0; i < len; i+=4)
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*(u32*)&data[i] = SRAMStatus * 0x01010101;
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}
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return 0;
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default:
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/*if (cmd[0] != 0xB8)
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printf("shitty command %02X %02X %02X %02X %02X %02X %02X %02X - %08X\n",
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cmd[0], cmd[1], cmd[2], cmd[3],
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cmd[4], cmd[5], cmd[6], cmd[7], len);*/
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return CartRetail::ROMCommandStart(cmd, data, len);
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}
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}
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@ -1316,7 +1346,16 @@ void CartRetailNAND::ROMCommandFinish(u8* cmd, u8* data, u32 len)
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{
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switch (cmd[0])
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{
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// TODO!
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case 0x81: // write data
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if (SRAMAddr)
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{
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if ((SRAMWritePos + len) > 0x800)
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len = 0x800 - SRAMWritePos;
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memcpy(&SRAMWriteBuffer[SRAMWritePos], data, len);
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SRAMWritePos += len;
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}
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return;
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default:
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return CartCommon::ROMCommandFinish(cmd, data, len);
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@ -155,7 +155,11 @@ public:
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u8 SPIWrite(u8 val, u32 pos, bool last);
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private:
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u32 SRAMReadWindow;
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u32 SRAMBase;
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u32 SRAMWindow;
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u8 SRAMWriteBuffer[0x800];
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u32 SRAMWritePos;
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};
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// CartRetailIR -- SPI IR device and SRAM
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