diff --git a/src/ARM.h b/src/ARM.h index c6711333..64921654 100644 --- a/src/ARM.h +++ b/src/ARM.h @@ -313,6 +313,7 @@ public: void ICacheLookup(u32 addr); void ICacheInvalidateByAddr(u32 addr); void ICacheInvalidateAll(); + bool IsAddressICachable(u32 addr); void CP15Write(u32 id, u32 val); u32 CP15Read(u32 id) const; diff --git a/src/CP15.cpp b/src/CP15.cpp index 916f1631..0573f974 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -417,6 +417,11 @@ void ARMv5::ICacheInvalidateAll() ICacheTags[i] = 1; } +bool ARMv5::IsAddressICachable(u32 addr) +{ + return PU_Map[addr >> 12] & 0x40 ; +} + void ARMv5::CP15Write(u32 id, u32 val) { @@ -430,7 +435,7 @@ void ARMv5::CP15Write(u32 id, u32 val) val &= 0x000FF085; CP15Control &= ~0x000FF085; CP15Control |= val; - //printf("CP15Control = %08X (%08X->%08X)\n", CP15Control, old, val); + //Log(LogLevel::Debug, "CP15Control = %08X (%08X->%08X)\n", CP15Control, old, val); UpdateDTCMSetting(); UpdateITCMSetting(); if ((old & 0x1005) != (val & 0x1005)) @@ -800,6 +805,7 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch) } CodeCycles = RegionCodeCycles; +#if 0 if (CodeCycles == 0xFF) // cached memory. hax { if (branch || !(addr & 0x1F)) @@ -809,6 +815,16 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch) //return *(u32*)&CurICacheLine[addr & 0x1C]; } +#else + if (CP15Control & CP15_CACHE_CR_ICACHEENABLE) + { + if (IsAddressICachable(addr)) + { + ICacheLookup(addr); + return *(u32*)&CurICacheLine[addr & (ICACHE_LINELENGTH - 4)]; + } + } +#endif if (CodeMem.Mem) return *(u32*)&CodeMem.Mem[addr & CodeMem.Mask]; diff --git a/src/MemConstants.h b/src/MemConstants.h index ccd1ea00..fbb37523 100644 --- a/src/MemConstants.h +++ b/src/MemConstants.h @@ -44,10 +44,11 @@ constexpr u32 ICACHE_LINELENGTH_LOG2 = ICACHE_LINELENGTH_ENCODED + 3; constexpr u32 ICACHE_LINELENGTH = 8 * (1 << ICACHE_LINELENGTH_ENCODED); constexpr u32 ICACHE_LINESPERSET = ICACHE_SIZE / (ICACHE_SETS * ICACHE_LINELENGTH); -constexpr u32 CP15_CACHE_CR_ROUNDROBIN = (1 < 14); -constexpr u32 CP15_CACHE_CR_ICACHEENABLE = (1 < 12); -constexpr u32 CP15_CACHE_CR_DCACHEENABLE = (1 < 2); -constexpr u32 CP15_CACHE_CR_WRITEBUFFERENABLE = (1 < 3); +constexpr u32 CP15_CR_MPUENABLE = (1 << 0); +constexpr u32 CP15_CACHE_CR_ROUNDROBIN = (1 << 14); +constexpr u32 CP15_CACHE_CR_ICACHEENABLE = (1 << 12); +constexpr u32 CP15_CACHE_CR_DCACHEENABLE = (1 << 2); +constexpr u32 CP15_CACHE_CR_WRITEBUFFERENABLE = (1 << 3); } #endif // MELONDS_MEMCONSTANTS_H \ No newline at end of file