Fixed an issue with caclulating DTCM/ITCM masks after addr was declared constant
Encapsuled the cache features in #if to disable the features via compile flags
This commit is contained in:
DesperateProgrammer
parent
a8306f2aa0
commit
4164687bd2
73
src/CP15.cpp
73
src/CP15.cpp
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@ -623,10 +623,11 @@ u32 ARMv5::DCacheLookup(const u32 addr)
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u32* ptr = (u32 *)&DCache[line << DCACHE_LINELENGTH_LOG2];
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DataCycles = 0;
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#if !DISABLE_CACHEWRITEBACK
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// Before we fill the cacheline, we need to write back dirty content
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// Datacycles will be incremented by the required cycles to do so
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DCacheClearByASetAndWay(line & (DCACHE_SETS-1), line >> DCACHE_SETS_LOG2);
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#endif
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//Log(LogLevel::Debug,"DCache miss, load @ %08x\n", tag);
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for (int i = 0; i < DCACHE_LINELENGTH; i+=sizeof(u32))
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{
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@ -667,7 +668,8 @@ bool ARMv5::DCacheWrite32(const u32 addr, const u32 val)
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u32 *cacheLine = (u32 *)&DCache[(id+set) << DCACHE_LINELENGTH_LOG2];
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cacheLine[(addr & (DCACHE_LINELENGTH-1)) >> 2] = val;
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DataCycles = 1;
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//if (PU_Map[addr >> CP15_MAP_ENTRYSIZE_LOG2] & CP15_MAP_DCACHEWRITEBACK)
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#if !DISABLE_CACHEWRITEBACK
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if (PU_Map[addr >> CP15_MAP_ENTRYSIZE_LOG2] & CP15_MAP_DCACHEWRITEBACK)
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{
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if (addr & (DCACHE_LINELENGTH / 2))
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{
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@ -680,6 +682,7 @@ bool ARMv5::DCacheWrite32(const u32 addr, const u32 val)
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// just mark dirty and abort the data write through the bus
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return true;
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}
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#endif
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return false;
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}
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}
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@ -699,7 +702,8 @@ bool ARMv5::DCacheWrite16(const u32 addr, const u16 val)
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u16 *cacheLine = (u16 *)&DCache[(id+set) << DCACHE_LINELENGTH_LOG2];
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cacheLine[(addr & (DCACHE_LINELENGTH-1)) >> 1] = val;
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DataCycles = 1;
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//if (PU_Map[addr >> CP15_MAP_ENTRYSIZE_LOG2] & CP15_MAP_DCACHEWRITEBACK)
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#if !DISABLE_CACHEWRITEBACK
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if (PU_Map[addr >> CP15_MAP_ENTRYSIZE_LOG2] & CP15_MAP_DCACHEWRITEBACK)
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{
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if (addr & (DCACHE_LINELENGTH / 2))
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{
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@ -712,6 +716,7 @@ bool ARMv5::DCacheWrite16(const u32 addr, const u16 val)
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// just mark dirtyand abort the data write through the bus
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return true;
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}
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#endif
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return false;
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}
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}
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@ -732,7 +737,8 @@ bool ARMv5::DCacheWrite8(const u32 addr, const u8 val)
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u8 *cacheLine = &DCache[(id+set) << DCACHE_LINELENGTH_LOG2];
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cacheLine[addr & (DCACHE_LINELENGTH-1)] = val;
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DataCycles = 1;
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//if (PU_Map[addr >> CP15_MAP_ENTRYSIZE_LOG2] & CP15_MAP_DCACHEWRITEBACK)
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#if !DISABLE_CACHEWRITEBACK
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if (PU_Map[addr >> CP15_MAP_ENTRYSIZE_LOG2] & CP15_MAP_DCACHEWRITEBACK)
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{
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if (addr & (DCACHE_LINELENGTH / 2))
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{
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@ -746,6 +752,7 @@ bool ARMv5::DCacheWrite8(const u32 addr, const u8 val)
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// just mark dirty and abort the data write through the bus
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return true;
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}
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#endif
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return false;
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}
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}
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@ -789,13 +796,16 @@ void ARMv5::DCacheInvalidateAll()
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void ARMv5::DCacheClearAll()
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{
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#if !DISABLE_CACHEWRITEBACK
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for (int set = 0;set<DCACHE_SETS;set++)
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for (int line = 0;line<=DCACHE_LINESPERSET;line++)
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DCacheClearByASetAndWay(set, line);
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#endif
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}
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void ARMv5::DCacheClearByAddr(const u32 addr)
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{
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#if !DISABLE_CACHEWRITEBACK
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const u32 tag = (addr & ~(DCACHE_LINELENGTH - 1)) | CACHE_FLAG_VALID;
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const u32 id = ((addr >> DCACHE_LINELENGTH_LOG2) & (DCACHE_LINESPERSET-1)) << DCACHE_SETS_LOG2;
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@ -807,10 +817,12 @@ void ARMv5::DCacheClearByAddr(const u32 addr)
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return;
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}
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}
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#endif
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}
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void ARMv5::DCacheClearByASetAndWay(const u8 cacheSet, const u8 cacheLine)
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{
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#if !DISABLE_CACHEWRITEBACK
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const u32 index = cacheSet | (cacheLine << DCACHE_SETS_LOG2);
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// Only write back if valid
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@ -863,6 +875,7 @@ void ARMv5::DCacheClearByASetAndWay(const u8 cacheSet, const u8 cacheLine)
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DataCycles += (NDS.ARM9MemTimings[tag >> 14][2] + (NDS.ARM9MemTimings[tag >> 14][3] * ((DCACHE_LINELENGTH / 8) - 1))) << NDS.ARM9ClockShift;
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}
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DCacheTags[index] &= ~(CACHE_FLAG_DIRTY_LOWERHALF | CACHE_FLAG_DIRTY_UPPERHALF);
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#endif
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}
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bool ARMv5::IsAddressDCachable(const u32 addr) const
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@ -898,7 +911,7 @@ void ARMv5::CP15Write(const u32 id, const u32 val)
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{
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u32 diff = PU_DataCacheable ^ val;
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PU_DataCacheable = val;
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#if 0
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#if 1
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// This code just updates the PU_Map entries of the given region
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// this works fine, if the regions do not overlap
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// If overlapping and the least priority region cachable bit
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@ -924,7 +937,7 @@ void ARMv5::CP15Write(const u32 id, const u32 val)
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{
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u32 diff = PU_CodeCacheable ^ val;
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PU_CodeCacheable = val;
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#if 0
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#if 1
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// This code just updates the PU_Map entries of the given region
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// this works fine, if the regions do not overlap
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// If overlapping and the least priority region cachable bit
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@ -951,7 +964,7 @@ void ARMv5::CP15Write(const u32 id, const u32 val)
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{
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u32 diff = PU_DataCacheWrite ^ val;
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PU_DataCacheWrite = val;
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#if 0
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#if 1
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// This code just updates the PU_Map entries of the given region
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// this works fine, if the regions do not overlap
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// If overlapping and the least priority region write buffer
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@ -983,7 +996,7 @@ void ARMv5::CP15Write(const u32 id, const u32 val)
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for (int i=0;i<CP15_REGION_COUNT;i++)
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PU_DataRW |= (val >> (i * 2) & 3) << (i * CP15_REGIONACCESS_BITS_PER_REGION);
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#if 0
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#if 1
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// This code just updates the PU_Map entries of the given region
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// this works fine, if the regions do not overlap
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// If overlapping and the least priority region access permission
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@ -1015,7 +1028,7 @@ void ARMv5::CP15Write(const u32 id, const u32 val)
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for (int i=0;i<CP15_REGION_COUNT;i++)
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PU_CodeRW |= (val >> (i * 2) & 3) << (i * CP15_REGIONACCESS_BITS_PER_REGION);
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#if 0
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#if 1
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// This code just updates the PU_Map entries of the given region
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// this works fine, if the regions do not overlap
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// If overlapping and the least priority region access permission
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@ -1041,7 +1054,7 @@ void ARMv5::CP15Write(const u32 id, const u32 val)
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{
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u32 diff = PU_DataRW ^ val;
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PU_DataRW = val;
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#if 0
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#if 1
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// This code just updates the PU_Map entries of the given region
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// this works fine, if the regions do not overlap
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// If overlapping and the least priority region access permission
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@ -1065,7 +1078,7 @@ void ARMv5::CP15Write(const u32 id, const u32 val)
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{
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u32 diff = PU_CodeRW ^ val;
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PU_CodeRW = val;
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#if 0
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#if 1
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// This code just updates the PU_Map entries of the given region
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// this works fine, if the regions do not overlap
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// If overlapping and the least priority region access permission
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@ -1399,7 +1412,7 @@ void ARMv5::CP15Write(const u32 id, const u32 val)
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uint8_t segment = (CacheDebugRegisterIndex >> (32-DCACHE_SETS_LOG2)) & (DCACHE_SETS-1);
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uint8_t wordAddress = (CacheDebugRegisterIndex & (DCACHE_LINELENGTH-1)) >> 2;
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uint8_t index = (CacheDebugRegisterIndex >> DCACHE_LINELENGTH_LOG2) & (DCACHE_LINESPERSET-1);
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*(u32 *)&DCache[((index << DCACHE_SETS_LOG2) + segment) << DCACHE_LINELENGTH_LOG2 + wordAddress*4] = val;
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*(u32 *)&DCache[(((index << DCACHE_SETS_LOG2) + segment) << DCACHE_LINELENGTH_LOG2) + wordAddress*4] = val;
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}
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return;
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@ -1488,7 +1501,7 @@ u32 ARMv5::CP15Read(const u32 id) const
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case 0x661:
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case 0x670:
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case 0x671:
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return PU_Region[(id >> CP15_REGIONACCESS_BITS_PER_REGION) & 0xF];
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return PU_Region[(id >> 4) & 0xF];
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case 0x7A6:
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// read Cache Dirty Bit (optional)
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@ -1585,6 +1598,7 @@ u32 ARMv5::CP15Read(const u32 id) const
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u32 ARMv5::CodeRead32(const u32 addr, bool const branch)
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{
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#if !DISABLE_ICACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1597,6 +1611,7 @@ u32 ARMv5::CodeRead32(const u32 addr, bool const branch)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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@ -1631,6 +1646,7 @@ void ARMv5::DataRead8(const u32 addr, u32* val)
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DataRegion = addr;
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#if !DISABLE_DCACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1644,6 +1660,7 @@ void ARMv5::DataRead8(const u32 addr, u32* val)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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@ -1673,6 +1690,7 @@ void ARMv5::DataRead16(const u32 addr, u32* val)
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DataRegion = addr;
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#if !DISABLE_DCACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1686,6 +1704,7 @@ void ARMv5::DataRead16(const u32 addr, u32* val)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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@ -1715,6 +1734,7 @@ void ARMv5::DataRead32(const u32 addr, u32* val)
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DataRegion = addr;
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#if !DISABLE_DCACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1728,17 +1748,18 @@ void ARMv5::DataRead32(const u32 addr, u32* val)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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DataCycles = 1;
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*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 3)];
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*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 4)];
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return;
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}
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if ((addr & DTCMMask) == DTCMBase)
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{
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DataCycles = 1;
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*val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 3)];
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*val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 4)];
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return;
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}
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@ -1748,6 +1769,7 @@ void ARMv5::DataRead32(const u32 addr, u32* val)
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void ARMv5::DataRead32S(const u32 addr, u32* val)
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{
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#if !DISABLE_DCACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1761,17 +1783,18 @@ void ARMv5::DataRead32S(const u32 addr, u32* val)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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DataCycles += 1;
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*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 3)];
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*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 4)];
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return;
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}
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if ((addr & DTCMMask) == DTCMBase)
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{
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DataCycles += 1;
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*val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 3)];
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*val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 4)];
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return;
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}
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@ -1789,6 +1812,7 @@ void ARMv5::DataWrite8(const u32 addr, const u8 val)
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DataRegion = addr;
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#if !DISABLE_DCACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1802,6 +1826,7 @@ void ARMv5::DataWrite8(const u32 addr, const u8 val)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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@ -1831,6 +1856,7 @@ void ARMv5::DataWrite16(const u32 addr, const u16 val)
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DataRegion = addr;
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#if !DISABLE_DCACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1844,6 +1870,7 @@ void ARMv5::DataWrite16(const u32 addr, const u16 val)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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@ -1873,6 +1900,7 @@ void ARMv5::DataWrite32(const u32 addr, const u32 val)
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DataRegion = addr;
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#if !DISABLE_DCACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1886,18 +1914,19 @@ void ARMv5::DataWrite32(const u32 addr, const u32 val)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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DataCycles = 1;
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*(u32*)&ITCM[addr & (ITCMPhysicalSize - 3)] = val;
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*(u32*)&ITCM[addr & (ITCMPhysicalSize - 4)] = val;
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
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return;
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}
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if ((addr & DTCMMask) == DTCMBase)
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{
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DataCycles = 1;
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*(u32*)&DTCM[addr & (DTCMPhysicalSize - 3)] = val;
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*(u32*)&DTCM[addr & (DTCMPhysicalSize - 4)] = val;
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return;
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}
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@ -1907,6 +1936,7 @@ void ARMv5::DataWrite32(const u32 addr, const u32 val)
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void ARMv5::DataWrite32S(const u32 addr, const u32 val)
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{
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#if !DISABLE_DCACHE
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#ifdef JIT_ENABLED
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if (!NDS.IsJITEnabled())
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#endif
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@ -1920,11 +1950,12 @@ void ARMv5::DataWrite32S(const u32 addr, const u32 val)
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}
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}
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}
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#endif
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if (addr < ITCMSize)
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{
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DataCycles += 1;
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*(u32*)&ITCM[addr & (ITCMPhysicalSize - 3)] = val;
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*(u32*)&ITCM[addr & (ITCMPhysicalSize - 4)] = val;
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#ifdef JIT_ENABLED
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NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
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#endif
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@ -1933,7 +1964,7 @@ void ARMv5::DataWrite32S(const u32 addr, const u32 val)
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if ((addr & DTCMMask) == DTCMBase)
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{
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DataCycles += 1;
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*(u32*)&DTCM[addr & (DTCMPhysicalSize - 3)] = val;
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*(u32*)&DTCM[addr & (DTCMPhysicalSize - 4)] = val;
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return;
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}
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