Merge branch 'interpreter-fixes' into chemical-x

src/ARM.cpp

@@ -249,7 +249,7 @@ void ARM::DoSavestate(Savestate* file)
     file->VarArray(R_ABT, 3*sizeof(u32));
     file->VarArray(R_IRQ, 3*sizeof(u32));
     file->VarArray(R_UND, 3*sizeof(u32));
-    file->Var32(&CurInstr);
+    file->Var64(&CurInstr);
 #ifdef JIT_ENABLED
     if (file->Saving && NDS.IsJITEnabled())
     {
@@ -259,7 +259,7 @@ void ARM::DoSavestate(Savestate* file)
         FillPipeline();
     }
 #endif
-    file->VarArray(NextInstr, 2*sizeof(u32));
+    file->VarArray(NextInstr, 2*sizeof(u64));
 
     file->Var32(&ExceptionBase);
 
@@ -684,7 +684,7 @@ void ARMv5::Execute()
                 PC = R[15];
 
                 if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>();
-                else if (!(PU_Map[(R[15]-4)>>12] & 0x04)) [[unlikely]] // handle aborted instructions
+                else if (CurInstr & ((u64)1<<63)) [[unlikely]] // handle aborted instructions
                 {
                     PrefetchAbort();
                 }
@@ -708,7 +708,7 @@ void ARMv5::Execute()
                 PC = R[15];
 
                 if (IRQ && !(CPSR & 0x80)) TriggerIRQ<mode>();
-                else if (!(PU_Map[(R[15]-8)>>12] & 0x04)) [[unlikely]] // handle aborted instructions
+                else if (CurInstr & ((u64)1<<63)) [[unlikely]] // handle aborted instructions
                 {
                     PrefetchAbort();
                 }

src/ARM.h

@@ -178,8 +178,8 @@ public:
     u32 R_ABT[3];
     u32 R_IRQ[3];
     u32 R_UND[3];
-    u32 CurInstr;
-    u32 NextInstr[2];
+    u64 CurInstr;
+    u64 NextInstr[2];
 
     u32 ExceptionBase;
 
@@ -254,7 +254,7 @@ public:
     void Execute();
 
     // all code accesses are forced nonseq 32bit
-    u32 CodeRead32(const u32 addr, const bool branch);
+    u64 CodeRead32(const u32 addr, const bool branch);
 
     bool DataRead8(u32 addr, u32* val) override;
     bool DataRead16(u32 addr, u32* val) override;

src/ARMInterpreter.cpp

@@ -131,7 +131,7 @@ void A_MSR_IMM(ARM* cpu)
 
     if (cpu->CPSR & 0x20) [[unlikely]]
     {
-        if (cpu->Num == 0) cpu->NextInstr[1] &= 0xFFFF; // checkme: probably not the right way to handle this
+        if (cpu->Num == 0) cpu->R[15] += 2; // pc should actually increment by 4 one more time after switching to thumb mode without a pipeline flush, this gets the same effect.
         else
         {
             Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: MSR REG T bit change on ARM7\n");
@@ -203,7 +203,7 @@ void A_MSR_REG(ARM* cpu)
 
     if (cpu->CPSR & 0x20) [[unlikely]]
     {
-        if (cpu->Num == 0) cpu->NextInstr[1] &= 0xFFFF; // checkme: probably not the right way to handle this
+        if (cpu->Num == 0) cpu->R[15] += 2; // pc should actually increment by 4 one more time after switching to thumb mode without a pipeline flush, this gets the same effect.
         else
         {
             Platform::Log(Platform::LogLevel::Warn, "UNIMPLEMENTED: MSR REG T bit change on ARM7\n");

src/ARMJIT.cpp

@@ -588,7 +588,7 @@ void ARMJIT::CompileBlock(ARM* cpu) noexcept
     u32 numWriteAddrs = 0, writeAddrsTranslated = 0;
 
     cpu->FillPipeline();
-    u32 nextInstr[2] = {cpu->NextInstr[0], cpu->NextInstr[1]};
+    u32 nextInstr[2] = {(u32)cpu->NextInstr[0], (u32)cpu->NextInstr[1]};
     u32 nextInstrAddr[2] = {blockAddr, r15};
 
     JIT_DEBUGPRINT("start block %x %08x (%x)\n", blockAddr, cpu->CPSR, localAddr);

src/CP15.cpp

@@ -2057,7 +2057,7 @@ u32 ARMv5::CP15Read(const u32 id) const
 // TCM are handled here.
 // TODO: later on, handle PU
 
-u32 ARMv5::CodeRead32(u32 addr, bool branch)
+u64 ARMv5::CodeRead32(u32 addr, bool branch)
 {
     // prefetch abort
     // the actual exception is not raised until the aborted instruction is executed
@@ -2067,7 +2067,7 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
         if (NDS.ARM9Timestamp < TimestampActual) NDS.ARM9Timestamp = TimestampActual;
         DataRegion = Mem9_Null;
         Store = false;
-        return 0;
+        return ((u64)1<<63);
     }
 
     if (addr < ITCMSize)