diff --git a/src/ARM.cpp b/src/ARM.cpp
index 7bfb95a2..906a243e 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -177,8 +177,6 @@ void ARM::Reset()
 
     ExceptionBase = Num ? 0x00000000 : 0xFFFF0000;
 
-    BuggyJump = 0;
-
     CodeMem.Mem = NULL;
 
 #ifdef JIT_ENABLED
diff --git a/src/ARM.h b/src/ARM.h
index 9b0511a3..7c5bb671 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -64,7 +64,7 @@ public:
     virtual void DoSavestate(Savestate* file);
 
     virtual void FillPipeline() = 0;
-    
+
     virtual void JumpTo(u32 addr, bool restorecpsr = false) = 0;
     virtual void JumpTo8_16Bit(u32 addr) = 0;
     void RestoreCPSR();
@@ -174,7 +174,6 @@ public:
     u32 R_UND[3];
     u32 CurInstr;
     u32 NextInstr[2];
-    u32 BuggyJump;
 
     u32 ExceptionBase;
 
@@ -237,7 +236,7 @@ public:
     void UpdateRegionTimings(u32 addrstart, u32 addrend);
 
     void FillPipeline() override;
-    
+
     void JumpTo(u32 addr, bool restorecpsr = false) override;
     void JumpTo8_16Bit(const u32 addr) override;
 
@@ -383,7 +382,7 @@ public:
     ARMv4(melonDS::NDS& nds, std::optional<GDBArgs> gdb, bool jit);
 
     void FillPipeline() override;
-    
+
     void JumpTo(u32 addr, bool restorecpsr = false) override;
     void JumpTo8_16Bit(const u32 addr) override;
 
diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index 1f43868f..2e841549 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -259,7 +259,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     if (cpu->Num != 0) return; \
     offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 r = (cpu->CurInstr>>12) & 0xF; \
-    if (r&1) { A_UNK(cpu); return; } /* checkme */ \
+    if (r&1) { A_UNK(cpu); return; } \
     if (!cpu->DataRead32 (offset  , &cpu->R[r  ])) {cpu->AddCycles_CDI(); return;} \
     u32 val; if (!cpu->DataRead32S(offset+4, &val)) {cpu->AddCycles_CDI(); return;} \
     if (r == 14) cpu->JumpTo(((((ARMv5*)cpu)->CP15Control & (1<<15)) ? (val & ~0x1) : val), cpu->CurInstr & (1<<22)); /* restores cpsr due to shared ldm dna */ \
@@ -271,7 +271,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     if (cpu->Num != 0) return; \
     u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 r = (cpu->CurInstr>>12) & 0xF; \
-    if (r&1) { A_UNK(cpu); return; } /* checkme */ \
+    if (r&1) { A_UNK(cpu); return; } \
     if (!cpu->DataRead32 (addr  , &cpu->R[r  ])) {cpu->AddCycles_CDI(); return;} \
     u32 val; if (!cpu->DataRead32S(addr+4, &val)) {cpu->AddCycles_CDI(); return;} \
     if (r == 14) cpu->JumpTo(((((ARMv5*)cpu)->CP15Control & (1<<15)) ? (val & ~0x1) : val), cpu->CurInstr & (1<<22)); /* restores cpsr due to shared ldm dna */ \
@@ -283,7 +283,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     if (cpu->Num != 0) return; \
     offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 r = (cpu->CurInstr>>12) & 0xF; \
-    if (r&1) { A_UNK(cpu); return; } /* checkme */ \
+    if (r&1) { A_UNK(cpu); return; } \
     bool dataabort = !cpu->DataWrite32(offset, cpu->R[r]); /* yes, this data abort behavior is on purpose */ \
     u32 storeval = cpu->R[r+1]; if (r == 14) storeval+=4; \
     dataabort |= !cpu->DataWrite32S (offset+4, storeval, dataabort); /* no, i dont understand it either */ \
@@ -295,7 +295,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     if (cpu->Num != 0) return; \
     u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
     u32 r = (cpu->CurInstr>>12) & 0xF; \
-    if (r&1) { A_UNK(cpu); return; } /* checkme */ \
+    if (r&1) { A_UNK(cpu); return; } \
     bool dataabort = !cpu->DataWrite32(addr, cpu->R[r]); \
     u32 storeval = cpu->R[r+1]; if (r == 14) storeval+=4; \
     dataabort |= !cpu->DataWrite32S (addr+4, storeval, dataabort); \