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tcms just aren't bufferable

This commit is contained in:
Jaklyy 2024-10-10 22:54:33 -04:00
parent 34bba2589e
commit 3d246ddf73
1 changed files with 85 additions and 160 deletions
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109
src/CP15.cpp
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@ -450,43 +450,19 @@ void ARMv5::WriteBufferCheck()
case 0: // byte case 0: // byte
{ {
u8 val = WriteBufferFifo[WBWritePointer] & 0xFF; u8 val = WriteBufferFifo[WBWritePointer] & 0xFF;
if (WBAddr < ITCMSize) BusWrite8(storeaddr[WBWritePointer], val);
{
*(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val;
else BusWrite8(storeaddr[WBWritePointer], val);
break; break;
} }
case 1: // halfword case 1: // halfword
{ {
u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF; u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF;
if (WBAddr < ITCMSize) BusWrite16(storeaddr[WBWritePointer], val);
{
*(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val;
else BusWrite16(storeaddr[WBWritePointer], val);
break; break;
} }
case 2: // word case 2: // word
{ {
u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
if (WBAddr < ITCMSize) BusWrite32(storeaddr[WBWritePointer], val);
{
*(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val;
else BusWrite32(storeaddr[WBWritePointer], val);
WBAddr += 4; WBAddr += 4;
break; break;
} }
@ -523,43 +499,19 @@ void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr)
case 0: // byte case 0: // byte
{ {
u8 val = WriteBufferFifo[WBWritePointer] & 0xFF; u8 val = WriteBufferFifo[WBWritePointer] & 0xFF;
if (WBAddr < ITCMSize) BusWrite8(storeaddr[WBWritePointer], val);
{
*(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val;
else BusWrite8(storeaddr[WBWritePointer], val);
break; break;
} }
case 1: // halfword case 1: // halfword
{ {
u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF; u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF;
if (WBAddr < ITCMSize) BusWrite16(storeaddr[WBWritePointer], val);
{
*(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val;
else BusWrite16(storeaddr[WBWritePointer], val);
break; break;
} }
case 2: // word case 2: // word
{ {
u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
if (WBAddr < ITCMSize) BusWrite32(storeaddr[WBWritePointer], val);
{
*(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val;
else BusWrite32(storeaddr[WBWritePointer], val);
WBAddr += 4; WBAddr += 4;
break; break;
} }
@ -609,43 +561,19 @@ void ARMv5::WriteBufferDrain()
case 0: // byte case 0: // byte
{ {
u8 val = WriteBufferFifo[WBWritePointer] & 0xFF; u8 val = WriteBufferFifo[WBWritePointer] & 0xFF;
if (WBAddr < ITCMSize) BusWrite8(storeaddr[WBWritePointer], val);
{
*(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val;
else BusWrite8(storeaddr[WBWritePointer], val);
break; break;
} }
case 1: // halfword case 1: // halfword
{ {
u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF; u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF;
if (WBAddr < ITCMSize) BusWrite16(storeaddr[WBWritePointer], val);
{
*(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val;
else BusWrite16(storeaddr[WBWritePointer], val);
break; break;
} }
case 2: // word case 2: // word
{ {
u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF;
if (WBAddr < ITCMSize) BusWrite32(storeaddr[WBWritePointer], val);
{
*(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val;
#ifdef JIT_ENABLED
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr);
#endif
}
else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val;
else BusWrite32(storeaddr[WBWritePointer], val);
WBAddr += 4; WBAddr += 4;
break; break;
} }
@ -1255,8 +1183,6 @@ bool ARMv5::DataWrite8(u32 addr, u8 val)
return false; return false;
} }
if (!(PU_Map[addr>>12] & (0x30)))
{
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
DataCycles = 1; DataCycles = 1;
@ -1276,6 +1202,8 @@ bool ARMv5::DataWrite8(u32 addr, u8 val)
return true; return true;
} }
if (!(PU_Map[addr>>12] & (0x30)))
{
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1); NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
DataCycles = MemTimings[addr >> 12][1]; DataCycles = MemTimings[addr >> 12][1];
@ -1315,9 +1243,6 @@ bool ARMv5::DataWrite16(u32 addr, u16 val)
addr &= ~1; addr &= ~1;
if (!(PU_Map[addr>>12] & 0x30))
{
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
DataCycles = 1; DataCycles = 1;
@ -1337,6 +1262,8 @@ bool ARMv5::DataWrite16(u32 addr, u16 val)
return true; return true;
} }
if (!(PU_Map[addr>>12] & 0x30))
{
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1); NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
DataCycles = MemTimings[addr >> 12][1]; DataCycles = MemTimings[addr >> 12][1];
@ -1376,9 +1303,6 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
addr &= ~3; addr &= ~3;
if (!(PU_Map[addr>>12] & 0x30))
{
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
DataCycles = 1; DataCycles = 1;
@ -1398,6 +1322,8 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
return true; return true;
} }
if (!(PU_Map[addr>>12] & 0x30))
{
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1); NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
DataCycles = MemTimings[addr >> 12][2]; DataCycles = MemTimings[addr >> 12][2];
@ -1436,9 +1362,6 @@ bool ARMv5::DataWrite32S(u32 addr, u32 val)
addr &= ~3; addr &= ~3;
if (!(PU_Map[addr>>12] & 0x30))
{
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
DataCycles += 1; DataCycles += 1;
@ -1458,6 +1381,8 @@ bool ARMv5::DataWrite32S(u32 addr, u32 val)
return true; return true;
} }
if (!(PU_Map[addr>>12] & 0x30))
{
DataCycles += (((NDS.ARM9Timestamp + DataCycles) + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1)) - (NDS.ARM9Timestamp + DataCycles)); DataCycles += (((NDS.ARM9Timestamp + DataCycles) + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1)) - (NDS.ARM9Timestamp + DataCycles));
if (!(addr & 0x3FF)) return DataWrite32(addr, val); // bursts cannot cross a 1kb boundary if (!(addr & 0x3FF)) return DataWrite32(addr, val); // bursts cannot cross a 1kb boundary