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tcm (and cache?) reads dont trigger write buffer drains 

additionally drains are triggered even in no cache + no buffer regions despite documentation not specifying such
This commit is contained in:
Jaklyy 2024-10-10 20:51:52 -04:00
parent 5c120f45ee
commit 34bba2589e
1 changed files with 10 additions and 14 deletions
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24
src/CP15.cpp
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@ -1014,9 +1014,6 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
return 0; return 0;
} }
if ((PU_Map[addr>>12] & 0x30))
WriteBufferDrain();
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
CodeCycles = 1; CodeCycles = 1;
@ -1039,6 +1036,8 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
//return *(u32*)&CurICacheLine[addr & 0x1C]; //return *(u32*)&CurICacheLine[addr & 0x1C];
} }
WriteBufferDrain();
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1); NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
if ((addr >> 24) == 0x02) if ((addr >> 24) == 0x02)
@ -1067,9 +1066,6 @@ bool ARMv5::DataRead8(u32 addr, u32* val)
return false; return false;
} }
if ((PU_Map[addr>>12] & 0x30))
WriteBufferDrain();
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
DataCycles = 1; DataCycles = 1;
@ -1086,6 +1082,8 @@ bool ARMv5::DataRead8(u32 addr, u32* val)
return true; return true;
} }
WriteBufferDrain();
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1); NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
DataCycles = MemTimings[addr >> 12][1]; DataCycles = MemTimings[addr >> 12][1];
@ -1114,8 +1112,6 @@ bool ARMv5::DataRead16(u32 addr, u32* val)
} }
addr &= ~1; addr &= ~1;
if ((PU_Map[addr>>12] & 0x30))
WriteBufferDrain();
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
@ -1133,6 +1129,8 @@ bool ARMv5::DataRead16(u32 addr, u32* val)
return true; return true;
} }
WriteBufferDrain();
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1); NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
DataCycles = MemTimings[addr >> 12][1]; DataCycles = MemTimings[addr >> 12][1];
@ -1162,9 +1160,6 @@ bool ARMv5::DataRead32(u32 addr, u32* val)
addr &= ~3; addr &= ~3;
if ((PU_Map[addr>>12] & 0x30))
WriteBufferDrain();
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
DataCycles = 1; DataCycles = 1;
@ -1181,6 +1176,8 @@ bool ARMv5::DataRead32(u32 addr, u32* val)
return true; return true;
} }
WriteBufferDrain();
NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1); NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<<NDS.ARM9ClockShift)-1) & ~((1<<NDS.ARM9ClockShift)-1);
DataCycles = MemTimings[addr >> 12][2]; DataCycles = MemTimings[addr >> 12][2];
@ -1209,9 +1206,6 @@ bool ARMv5::DataRead32S(u32 addr, u32* val)
addr &= ~3; addr &= ~3;
if ((PU_Map[addr>>12] & 0x30))
WriteBufferDrain();
if (addr < ITCMSize) if (addr < ITCMSize)
{ {
DataCycles += 1; DataCycles += 1;
@ -1228,6 +1222,8 @@ bool ARMv5::DataRead32S(u32 addr, u32* val)
return true; return true;
} }
WriteBufferDrain();
NDS.ARM9Timestamp += DataCycles; NDS.ARM9Timestamp += DataCycles;
if (!(addr & 0x3FF)) return DataRead32(addr, val); // bursts cannot cross a 1kb boundary if (!(addr & 0x3FF)) return DataRead32(addr, val); // bursts cannot cross a 1kb boundary