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implement LDR/STR/LDRB/STRB. 

more macro soup.
This commit is contained in:
StapleButter 2016-12-03 01:31:33 +01:00
parent 97ec988dae
commit 23d584ca4c
8 changed files with 660 additions and 275 deletions
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83
ARM.h
View File

@ -55,10 +55,87 @@ public:
if (v) CPSR |= 0x10000000; if (v) CPSR |= 0x10000000;
} }
u32 Read32(u32 addr)
u8 Read8(u32 addr, u32 forceuser=0)
{ {
if (Num) return NDS::ARM7Read32(addr); if (!Num)
else return NDS::ARM9Read32(addr); {
// TODO: PU shit
return NDS::ARM9Read8(addr);
}
else
return NDS::ARM7Read8(addr);
}
u16 Read16(u32 addr, u32 forceuser=0)
{
addr &= ~1;
if (!Num)
{
// TODO: PU shit
return NDS::ARM9Read16(addr);
}
else
return NDS::ARM7Read16(addr);
}
u32 Read32(u32 addr, u32 forceuser=0)
{
addr &= ~3;
if (!Num)
{
// TODO: PU shit
return NDS::ARM9Read32(addr);
}
else
return NDS::ARM7Read32(addr);
}
void Write8(u32 addr, u8 val, u32 forceuser=0)
{
if (!Num)
{
// TODO: PU shit
NDS::ARM9Write8(addr, val);
}
else
NDS::ARM7Write8(addr, val);
}
void Write16(u32 addr, u16 val, u32 forceuser=0)
{
addr &= ~1;
if (!Num)
{
// TODO: PU shit
NDS::ARM9Write16(addr, val);
}
else
NDS::ARM7Write16(addr, val);
}
void Write32(u32 addr, u32 val, u32 forceuser=0)
{
addr &= ~3;
if (!Num)
{
// TODO: PU shit
NDS::ARM9Write32(addr, val);
}
else
NDS::ARM7Write32(addr, val);
}
s32 MemWaitstate(u32 type, u32 addr)
{
// type:
// 0 = code16
// 1 = code32
// 2 = data16
// 3 = data32
return 1; // sorry
} }

5
ARMInterpreter.cpp
View File

@ -3,6 +3,7 @@
#include "ARMInterpreter.h" #include "ARMInterpreter.h"
#include "ARMInterpreter_ALU.h" #include "ARMInterpreter_ALU.h"
#include "ARMInterpreter_Branch.h" #include "ARMInterpreter_Branch.h"
#include "ARMInterpreter_LoadStore.h"
namespace ARMInterpreter namespace ARMInterpreter
@ -11,7 +12,7 @@ namespace ARMInterpreter
s32 A_UNK(ARM* cpu) s32 A_UNK(ARM* cpu)
{ {
printf("undefined ARM instruction %08X @ %08X\n", cpu->CurInstr, cpu->R[15]-8); printf("undefined ARM%d instruction %08X @ %08X\n", cpu->Num?7:9, cpu->CurInstr, cpu->R[15]-8);
for (int i = 0; i < 16; i++) printf("R%d: %08X\n", i, cpu->R[i]); for (int i = 0; i < 16; i++) printf("R%d: %08X\n", i, cpu->R[i]);
NDS::Halt(); NDS::Halt();
return 0x7FFFFFFF; return 0x7FFFFFFF;
@ -19,7 +20,7 @@ s32 A_UNK(ARM* cpu)
s32 T_UNK(ARM* cpu) s32 T_UNK(ARM* cpu)
{ {
printf("undefined THUMB instruction %04X @ %08X\n", cpu->CurInstr, cpu->R[15]-4); printf("undefined THUMB%d instruction %04X @ %08X\n", cpu->Num?7:9, cpu->CurInstr, cpu->R[15]-4);
NDS::Halt(); NDS::Halt();
return 0x7FFFFFFF; return 0x7FFFFFFF;
} }

202
ARMInterpreter_LoadStore.cpp Normal file
View File

@ -0,0 +1,202 @@
#include "ARM.h"
namespace ARMInterpreter
{
// copypasta from ALU. bad
#define LSL_IMM(x, s) \
x <<= s;
#define LSR_IMM(x, s) \
if (s == 0) s = 32; \
x >>= s;
#define ASR_IMM(x, s) \
if (s == 0) s = 32; \
x = ((s32)x) >> s;
#define ROR_IMM(x, s) \
if (s == 0) \
{ \
x = (x >> 1) | ((cpu->CPSR & 0x20000000) << 2); \
} \
else \
{ \
x = ROR(x, s); \
}
#define A_WB_CALC_OFFSET_IMM \
u32 offset = (cpu->CurInstr & 0xFFF); \
if (!(cpu->CurInstr & (1<<23))) offset = -offset;
#define A_WB_CALC_OFFSET_REG(shiftop) \
u32 offset = cpu->R[cpu->CurInstr & 0xF]; \
u32 shift = ((cpu->CurInstr>>7)&0x1F); \
shiftop(offset, shift); \
if (!(cpu->CurInstr & (1<<23))) offset = -offset;
#define A_STR \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->Write32(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
return C_N(2) + cpu->MemWaitstate(3, offset);
#define A_STR_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->Write32(addr, cpu->R[(cpu->CurInstr>>12) & 0xF], cpu->CurInstr & (1<<21)); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
return C_N(2) + cpu->MemWaitstate(3, addr);
#define A_STRB \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->Write8(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
return C_N(2) + cpu->MemWaitstate(3, offset);
#define A_STRB_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->Write8(addr, cpu->R[(cpu->CurInstr>>12) & 0xF], cpu->CurInstr & (1<<21)); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
return C_N(2) + cpu->MemWaitstate(3, addr);
#define A_LDR \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 val = ROR(cpu->Read32(offset), offset&0x3); \
if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
if (cpu->Num==1) val &= ~0x1; \
cpu->JumpTo(val); \
return C_S(2) + C_N(2) + C_I(1) + cpu->MemWaitstate(3, offset); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = val; \
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset); \
}
#define A_LDR_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 val = ROR(cpu->Read32(addr, cpu->CurInstr & (1<<21)), addr&0x3); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
if (cpu->Num==1) val &= ~0x1; \
cpu->JumpTo(val); \
return C_S(2) + C_N(2) + C_I(1) + cpu->MemWaitstate(3, addr); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = val; \
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr); \
}
#define A_LDRB \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 val = cpu->Read8(offset); \
if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
cpu->R[(cpu->CurInstr>>12) & 0xF] = val; \
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset);
#define A_LDRB_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 val = cpu->Read8(addr, cpu->CurInstr & (1<<21)); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
cpu->R[(cpu->CurInstr>>12) & 0xF] = val; \
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
#define A_IMPLEMENT_WB_LDRSTR(x) \
\
s32 A_##x##_IMM(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_IMM \
A_##x \
} \
\
s32 A_##x##_REG_LSL(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_REG(LSL_IMM) \
A_##x \
} \
\
s32 A_##x##_REG_LSR(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_REG(LSR_IMM) \
A_##x \
} \
\
s32 A_##x##_REG_ASR(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_REG(ASR_IMM) \
A_##x \
} \
\
s32 A_##x##_REG_ROR(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_REG(ROR_IMM) \
A_##x \
} \
\
s32 A_##x##_POST_IMM(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_IMM \
A_##x##_POST \
} \
\
s32 A_##x##_POST_REG_LSL(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_REG(LSL_IMM) \
A_##x##_POST \
} \
\
s32 A_##x##_POST_REG_LSR(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_REG(LSR_IMM) \
A_##x##_POST \
} \
\
s32 A_##x##_POST_REG_ASR(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_REG(ASR_IMM) \
A_##x##_POST \
} \
\
s32 A_##x##_POST_REG_ROR(ARM* cpu) \
{ \
A_WB_CALC_OFFSET_REG(ROR_IMM) \
A_##x##_POST \
}
A_IMPLEMENT_WB_LDRSTR(STR)
A_IMPLEMENT_WB_LDRSTR(STRB)
A_IMPLEMENT_WB_LDRSTR(LDR)
A_IMPLEMENT_WB_LDRSTR(LDRB)
#define A_HD_CALC_OFFSET_IMM \
u32 offset = (cpu->CurInstr & 0xF) | ((cpu->CurInstr >> 4) & 0xF0); \
if (!(cpu->CurInstr & (1<<23))) offset = -offset;
#define A_HD_CALC_OFFSET_REG \
u32 offset = cpu->R[cpu->CurInstr & 0xF]; \
if (!(cpu->CurInstr & (1<<23))) offset = -offset;
#define A_STRH \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->Write16(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
}

29
ARMInterpreter_LoadStore.h Normal file
View File

@ -0,0 +1,29 @@
#ifndef ARMINTERPRETER_LOADSTORE_H
#define ARMINTERPRETER_LOADSTORE_H
namespace ARMInterpreter
{
#define A_PROTO_WB_LDRSTR(x) \
\
s32 A_##x##_IMM(ARM* cpu); \
s32 A_##x##_REG_LSL(ARM* cpu); \
s32 A_##x##_REG_LSR(ARM* cpu); \
s32 A_##x##_REG_ASR(ARM* cpu); \
s32 A_##x##_REG_ROR(ARM* cpu); \
s32 A_##x##_POST_IMM(ARM* cpu); \
s32 A_##x##_POST_REG_LSL(ARM* cpu); \
s32 A_##x##_POST_REG_LSR(ARM* cpu); \
s32 A_##x##_POST_REG_ASR(ARM* cpu); \
s32 A_##x##_POST_REG_ROR(ARM* cpu);
A_PROTO_WB_LDRSTR(STR)
A_PROTO_WB_LDRSTR(STRB)
A_PROTO_WB_LDRSTR(LDR)
A_PROTO_WB_LDRSTR(LDRB)
}
#endif

512
ARM_InstrTable.h
View File

@ -394,394 +394,394 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
// 0100 0000 0000 // 0100 0000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
// 0100 0001 0000 // 0100 0001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
// 0100 0010 0000 // 0100 0010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
// 0100 0011 0000 // 0100 0011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
// 0100 0100 0000 // 0100 0100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
// 0100 0101 0000 // 0100 0101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
// 0100 0110 0000 // 0100 0110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
// 0100 0111 0000 // 0100 0111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
// 0100 1000 0000 // 0100 1000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
// 0100 1001 0000 // 0100 1001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
// 0100 1010 0000 // 0100 1010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM, A_STR_POST_IMM,
// 0100 1011 0000 // 0100 1011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM, A_LDR_POST_IMM,
// 0100 1100 0000 // 0100 1100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
// 0100 1101 0000 // 0100 1101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
// 0100 1110 0000 // 0100 1110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM, A_STRB_POST_IMM,
// 0100 1111 0000 // 0100 1111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM, A_LDRB_POST_IMM,
// 0101 0000 0000 // 0101 0000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
// 0101 0001 0000 // 0101 0001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
// 0101 0010 0000 // 0101 0010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
// 0101 0011 0000 // 0101 0011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
// 0101 0100 0000 // 0101 0100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
// 0101 0101 0000 // 0101 0101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
// 0101 0110 0000 // 0101 0110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
// 0101 0111 0000 // 0101 0111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
// 0101 1000 0000 // 0101 1000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
// 0101 1001 0000 // 0101 1001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
// 0101 1010 0000 // 0101 1010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_IMM, A_STR_IMM, A_STR_IMM, A_STR_IMM,
// 0101 1011 0000 // 0101 1011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM, A_LDR_IMM,
// 0101 1100 0000 // 0101 1100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
// 0101 1101 0000 // 0101 1101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
// 0101 1110 0000 // 0101 1110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM, A_STRB_IMM,
// 0101 1111 0000 // 0101 1111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM, A_LDRB_IMM,
// 0110 0000 0000 // 0110 0000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_LSL, A_UNK, A_STR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_ASR, A_UNK, A_STR_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_LSL, A_UNK, A_STR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_ASR, A_UNK, A_STR_POST_REG_ROR, A_UNK,
// 0110 0001 0000 // 0110 0001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_LSL, A_UNK, A_LDR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_ASR, A_UNK, A_LDR_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_LSL, A_UNK, A_LDR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_ASR, A_UNK, A_LDR_POST_REG_ROR, A_UNK,
// 0110 0010 0000 // 0110 0010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_LSL, A_UNK, A_STR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_ASR, A_UNK, A_STR_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_LSL, A_UNK, A_STR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_ASR, A_UNK, A_STR_POST_REG_ROR, A_UNK,
// 0110 0011 0000 // 0110 0011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_LSL, A_UNK, A_LDR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_ASR, A_UNK, A_LDR_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_LSL, A_UNK, A_LDR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_ASR, A_UNK, A_LDR_POST_REG_ROR, A_UNK,
// 0110 0100 0000 // 0110 0100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_LSL, A_UNK, A_STRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_ASR, A_UNK, A_STRB_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_LSL, A_UNK, A_STRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_ASR, A_UNK, A_STRB_POST_REG_ROR, A_UNK,
// 0110 0101 0000 // 0110 0101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_LSL, A_UNK, A_LDRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_ASR, A_UNK, A_LDRB_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_LSL, A_UNK, A_LDRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_ASR, A_UNK, A_LDRB_POST_REG_ROR, A_UNK,
// 0110 0110 0000 // 0110 0110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_LSL, A_UNK, A_STRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_ASR, A_UNK, A_STRB_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_LSL, A_UNK, A_STRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_ASR, A_UNK, A_STRB_POST_REG_ROR, A_UNK,
// 0110 0111 0000 // 0110 0111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_LSL, A_UNK, A_LDRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_ASR, A_UNK, A_LDRB_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_LSL, A_UNK, A_LDRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_ASR, A_UNK, A_LDRB_POST_REG_ROR, A_UNK,
// 0110 1000 0000 // 0110 1000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_LSL, A_UNK, A_STR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_ASR, A_UNK, A_STR_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_LSL, A_UNK, A_STR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_ASR, A_UNK, A_STR_POST_REG_ROR, A_UNK,
// 0110 1001 0000 // 0110 1001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_LSL, A_UNK, A_LDR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_ASR, A_UNK, A_LDR_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_LSL, A_UNK, A_LDR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_ASR, A_UNK, A_LDR_POST_REG_ROR, A_UNK,
// 0110 1010 0000 // 0110 1010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_LSL, A_UNK, A_STR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_ASR, A_UNK, A_STR_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_LSL, A_UNK, A_STR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_POST_REG_ASR, A_UNK, A_STR_POST_REG_ROR, A_UNK,
// 0110 1011 0000 // 0110 1011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_LSL, A_UNK, A_LDR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_ASR, A_UNK, A_LDR_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_LSL, A_UNK, A_LDR_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_POST_REG_ASR, A_UNK, A_LDR_POST_REG_ROR, A_UNK,
// 0110 1100 0000 // 0110 1100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_LSL, A_UNK, A_STRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_ASR, A_UNK, A_STRB_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_LSL, A_UNK, A_STRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_ASR, A_UNK, A_STRB_POST_REG_ROR, A_UNK,
// 0110 1101 0000 // 0110 1101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_LSL, A_UNK, A_LDRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_ASR, A_UNK, A_LDRB_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_LSL, A_UNK, A_LDRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_ASR, A_UNK, A_LDRB_POST_REG_ROR, A_UNK,
// 0110 1110 0000 // 0110 1110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_LSL, A_UNK, A_STRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_ASR, A_UNK, A_STRB_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_LSL, A_UNK, A_STRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_POST_REG_ASR, A_UNK, A_STRB_POST_REG_ROR, A_UNK,
// 0110 1111 0000 // 0110 1111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_LSL, A_UNK, A_LDRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_ASR, A_UNK, A_LDRB_POST_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_LSL, A_UNK, A_LDRB_POST_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_POST_REG_ASR, A_UNK, A_LDRB_POST_REG_ROR, A_UNK,
// 0111 0000 0000 // 0111 0000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_LSL, A_UNK, A_STR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_ASR, A_UNK, A_STR_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_LSL, A_UNK, A_STR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_ASR, A_UNK, A_STR_REG_ROR, A_UNK,
// 0111 0001 0000 // 0111 0001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_LSL, A_UNK, A_LDR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_ASR, A_UNK, A_LDR_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_LSL, A_UNK, A_LDR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_ASR, A_UNK, A_LDR_REG_ROR, A_UNK,
// 0111 0010 0000 // 0111 0010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_LSL, A_UNK, A_STR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_ASR, A_UNK, A_STR_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_LSL, A_UNK, A_STR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_ASR, A_UNK, A_STR_REG_ROR, A_UNK,
// 0111 0011 0000 // 0111 0011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_LSL, A_UNK, A_LDR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_ASR, A_UNK, A_LDR_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_LSL, A_UNK, A_LDR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_ASR, A_UNK, A_LDR_REG_ROR, A_UNK,
// 0111 0100 0000 // 0111 0100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_LSL, A_UNK, A_STRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_ASR, A_UNK, A_STRB_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_LSL, A_UNK, A_STRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_ASR, A_UNK, A_STRB_REG_ROR, A_UNK,
// 0111 0101 0000 // 0111 0101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_LSL, A_UNK, A_LDRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_ASR, A_UNK, A_LDRB_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_LSL, A_UNK, A_LDRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_ASR, A_UNK, A_LDRB_REG_ROR, A_UNK,
// 0111 0110 0000 // 0111 0110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_LSL, A_UNK, A_STRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_ASR, A_UNK, A_STRB_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_LSL, A_UNK, A_STRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_ASR, A_UNK, A_STRB_REG_ROR, A_UNK,
// 0111 0111 0000 // 0111 0111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_LSL, A_UNK, A_LDRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_ASR, A_UNK, A_LDRB_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_LSL, A_UNK, A_LDRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_ASR, A_UNK, A_LDRB_REG_ROR, A_UNK,
// 0111 1000 0000 // 0111 1000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_LSL, A_UNK, A_STR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_ASR, A_UNK, A_STR_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_LSL, A_UNK, A_STR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_ASR, A_UNK, A_STR_REG_ROR, A_UNK,
// 0111 1001 0000 // 0111 1001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_LSL, A_UNK, A_LDR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_ASR, A_UNK, A_LDR_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_LSL, A_UNK, A_LDR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_ASR, A_UNK, A_LDR_REG_ROR, A_UNK,
// 0111 1010 0000 // 0111 1010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_LSL, A_UNK, A_STR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_ASR, A_UNK, A_STR_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_LSL, A_UNK, A_STR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STR_REG_ASR, A_UNK, A_STR_REG_ROR, A_UNK,
// 0111 1011 0000 // 0111 1011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_LSL, A_UNK, A_LDR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_ASR, A_UNK, A_LDR_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_LSL, A_UNK, A_LDR_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDR_REG_ASR, A_UNK, A_LDR_REG_ROR, A_UNK,
// 0111 1100 0000 // 0111 1100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_LSL, A_UNK, A_STRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_ASR, A_UNK, A_STRB_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_LSL, A_UNK, A_STRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_ASR, A_UNK, A_STRB_REG_ROR, A_UNK,
// 0111 1101 0000 // 0111 1101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_LSL, A_UNK, A_LDRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_ASR, A_UNK, A_LDRB_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_LSL, A_UNK, A_LDRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_ASR, A_UNK, A_LDRB_REG_ROR, A_UNK,
// 0111 1110 0000 // 0111 1110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_LSL, A_UNK, A_STRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_ASR, A_UNK, A_STRB_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_LSL, A_UNK, A_STRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_STRB_REG_ASR, A_UNK, A_STRB_REG_ROR, A_UNK,
// 0111 1111 0000 // 0111 1111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_LSL, A_UNK, A_LDRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_ASR, A_UNK, A_LDRB_REG_ROR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_LSL, A_UNK, A_LDRB_REG_LSR, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_LDRB_REG_ASR, A_UNK, A_LDRB_REG_ROR, A_UNK,

77
NDS.cpp
View File

@ -85,10 +85,31 @@ void Halt()
} }
u8 ARM9Read8(u32 addr)
{
if ((addr & 0xFFFFF000) == 0xFFFF0000)
{
return *(u8*)&ARM9BIOS[addr & 0xFFF];
}
printf("unknown arm9 read8 %08X\n", addr);
return 0;
}
u16 ARM9Read16(u32 addr)
{
if ((addr & 0xFFFFF000) == 0xFFFF0000)
{
return *(u16*)&ARM9BIOS[addr & 0xFFF];
}
printf("unknown arm9 read16 %08X\n", addr);
return 0;
}
u32 ARM9Read32(u32 addr) u32 ARM9Read32(u32 addr)
{ {
// implement ARM9y shit here, like memory protection
if ((addr & 0xFFFFF000) == 0xFFFF0000) if ((addr & 0xFFFFF000) == 0xFFFF0000)
{ {
return *(u32*)&ARM9BIOS[addr & 0xFFF]; return *(u32*)&ARM9BIOS[addr & 0xFFF];
@ -98,6 +119,45 @@ u32 ARM9Read32(u32 addr)
return 0; return 0;
} }
void ARM9Write8(u32 addr, u8 val)
{
printf("unknown arm9 write8 %08X %02X\n", addr, val);
}
void ARM9Write16(u32 addr, u16 val)
{
printf("unknown arm9 write16 %08X %04X\n", addr, val);
}
void ARM9Write32(u32 addr, u32 val)
{
printf("unknown arm9 write32 %08X %08X\n", addr, val);
}
u8 ARM7Read8(u32 addr)
{
if (addr < 0x00004000)
{
return *(u8*)&ARM7BIOS[addr];
}
printf("unknown arm7 read8 %08X\n", addr);
return 0;
}
u16 ARM7Read16(u32 addr)
{
if (addr < 0x00004000)
{
return *(u16*)&ARM7BIOS[addr];
}
printf("unknown arm7 read16 %08X\n", addr);
return 0;
}
u32 ARM7Read32(u32 addr) u32 ARM7Read32(u32 addr)
{ {
if (addr < 0x00004000) if (addr < 0x00004000)
@ -109,14 +169,19 @@ u32 ARM7Read32(u32 addr)
return 0; return 0;
} }
template<typename T> T Read(u32 addr) void ARM7Write8(u32 addr, u8 val)
{ {
return (T)0; printf("unknown arm7 write8 %08X %02X\n", addr, val);
} }
template<typename T> void Write(u32 addr, T val) void ARM7Write16(u32 addr, u16 val)
{ {
// printf("unknown arm7 write16 %08X %04X\n", addr, val);
}
void ARM7Write32(u32 addr, u32 val)
{
printf("unknown arm7 write32 %08X %08X\n", addr, val);
} }
} }

14
NDS.h
View File

@ -14,11 +14,19 @@ void RunFrame();
void Halt(); void Halt();
u8 ARM9Read8(u32 addr);
u16 ARM9Read16(u32 addr);
u32 ARM9Read32(u32 addr); u32 ARM9Read32(u32 addr);
u32 ARM7Read32(u32 addr); void ARM9Write8(u32 addr, u8 val);
void ARM9Write16(u32 addr, u16 val);
void ARM9Write32(u32 addr, u32 val);
template<typename T> T Read(u32 addr); u8 ARM7Read8(u32 addr);
template<typename T> void Write(u32 addr, T val); u16 ARM7Read16(u32 addr);
u32 ARM7Read32(u32 addr);
void ARM7Write8(u32 addr, u8 val);
void ARM7Write16(u32 addr, u16 val);
void ARM7Write32(u32 addr, u32 val);
} }

13
melonDS.depend
View File

@ -3,12 +3,12 @@
<stdio.h> <stdio.h>
"NDS.h" "NDS.h"
1480006838 c:\documents\sources\melonds\nds.h 1480030849 c:\documents\sources\melonds\nds.h
"types.h" "types.h"
1463409689 c:\documents\sources\melonds\types.h 1463409689 c:\documents\sources\melonds\types.h
1480007757 source:c:\documents\sources\melonds\nds.cpp 1480030786 source:c:\documents\sources\melonds\nds.cpp
<stdio.h> <stdio.h>
"NDS.h" "NDS.h"
"ARM.h" "ARM.h"
@ -19,22 +19,23 @@
"ARM.h" "ARM.h"
"ARMInterpreter.h" "ARMInterpreter.h"
1480027964 c:\documents\sources\melonds\arm.h 1480722720 c:\documents\sources\melonds\arm.h
"types.h" "types.h"
"NDS.h" "NDS.h"
1480028755 c:\documents\sources\melonds\arm_instrtable.h 1480724917 c:\documents\sources\melonds\arm_instrtable.h
1480018830 c:\documents\sources\melonds\arminterpreter.h 1480018830 c:\documents\sources\melonds\arminterpreter.h
"types.h" "types.h"
"ARM.h" "ARM.h"
1480015932 source:c:\documents\sources\melonds\arminterpreter.cpp 1480724944 source:c:\documents\sources\melonds\arminterpreter.cpp
<stdio.h> <stdio.h>
"NDS.h" "NDS.h"
"ARMInterpreter.h" "ARMInterpreter.h"
"ARMInterpreter_ALU.h" "ARMInterpreter_ALU.h"
"ARMInterpreter_Branch.h" "ARMInterpreter_Branch.h"
"ARMInterpreter_LoadStore.h"
"ARM_InstrTable.h" "ARM_InstrTable.h"
1480008608 c:\documents\sources\melonds\arminterpreter_branch.h 1480008608 c:\documents\sources\melonds\arminterpreter_branch.h
@ -47,3 +48,5 @@
1480028805 source:c:\documents\sources\melonds\arminterpreter_alu.cpp 1480028805 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
"ARM.h" "ARM.h"
1480724026 c:\documents\sources\melonds\arminterpreter_loadstore.h