From 6e30cf3bfb015a7372cbc24074adca2b526ea30c Mon Sep 17 00:00:00 2001 From: Jaklyy <102590697+Jaklyy@users.noreply.github.com> Date: Tue, 8 Oct 2024 17:18:09 -0400 Subject: [PATCH 1/3] functional write buffer prototype --- src/ARM.cpp | 7 +- src/ARM.h | 13 ++ src/CP15.cpp | 506 +++++++++++++++++++++++++++++++++++++++------------ 3 files changed, 406 insertions(+), 120 deletions(-) diff --git a/src/ARM.cpp b/src/ARM.cpp index d547174e..7072978d 100644 --- a/src/ARM.cpp +++ b/src/ARM.cpp @@ -208,6 +208,9 @@ void ARMv5::Reset() Store = false; InterlockMask = 0; + WBWritePointer = 16; + WBFillPointer = 0; + ARM::Reset(); } @@ -609,6 +612,7 @@ void ARMv5::Execute() else { NDS.ARM9Timestamp = NDS.ARM9Target; + WriteBufferCheck(); return; } } @@ -742,6 +746,7 @@ void ARMv5::Execute() //NDS.ARM9Timestamp += Cycles; //Cycles = 0; } + WriteBufferCheck(); if (Halted == 2) Halted = 0; @@ -757,7 +762,7 @@ void ARMv4::Execute() { if constexpr (mode == CPUExecuteMode::InterpreterGDB) GdbCheckB(); - + if (Halted) { if (Halted == 2) diff --git a/src/ARM.h b/src/ARM.h index 569f936a..12675023 100644 --- a/src/ARM.h +++ b/src/ARM.h @@ -291,11 +291,13 @@ public: void AddCycles_CDI() override { AddCycles_MW(DataCycles); + DataCycles = 0; } void AddCycles_CD() override { AddCycles_MW(DataCycles); + DataCycles = 0; } void GetCodeMemRegion(u32 addr, MemRegion* region); @@ -314,6 +316,10 @@ public: void ICacheLookup(u32 addr); void ICacheInvalidateByAddr(u32 addr); void ICacheInvalidateAll(); + + void WriteBufferCheck(); + void WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr = 0); + void WriteBufferDrain(); void CP15Write(u32 id, u32 val); u32 CP15Read(u32 id) const; @@ -369,6 +375,13 @@ public: bool Store; u16 InterlockMask; + u8 WBWritePointer; + u8 WBFillPointer; + u32 WBAddr; // current working address for the write buffer + u32 storeaddr[16]; // debugging + u64 WBCycles[16]; // timestamp each write will complete + u64 WriteBufferFifo[16]; // 0-31: value | 62-63: 0 byte, 1 half, 2 word, 3 addr + #ifdef GDBSTUB_ENABLED u32 ReadMem(u32 addr, int size) override; void WriteMem(u32 addr, int size, u32 v) override; diff --git a/src/CP15.cpp b/src/CP15.cpp index c83c5a49..613c1bd5 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -172,13 +172,13 @@ void ARMv5::UpdatePURegion(u32 n) if (CP15Control & (1<<2)) { datacache = (PU_DataCacheable >> n) & 0x1; - datawrite = (PU_DataCacheWrite >> n) & 0x1; } else { - datacache = 0; - datawrite = 0; + datacache = false; } + + datawrite = (PU_DataCacheWrite >> n) & 0x1; u32 rgn = PU_Region[n]; if (!(rgn & (1<<0))) @@ -224,12 +224,12 @@ void ARMv5::UpdatePURegion(u32 n) { privmask |= 0x10; usermask |= 0x10; - - if (datawrite & 0x1) - { - privmask |= 0x20; - usermask |= 0x20; - } + } + + if (datawrite & 0x1) + { + privmask |= 0x20; + usermask |= 0x20; } if (codecache & 0x1) @@ -438,6 +438,223 @@ void ARMv5::ICacheInvalidateAll() ICacheTags[i] = 1; } +void ARMv5::WriteBufferCheck() +{ + if (WBWritePointer == 16) return; + + while (WBCycles[WBWritePointer] <= (NDS.ARM9Timestamp + DataCycles)) + { + //printf("drainingwb %lli, %i %08X %i\n", WBCycles[WBWritePointer], WBWritePointer, WBAddr, WriteBufferFifo[WBWritePointer] >> 62); + switch ((u64)WriteBufferFifo[WBWritePointer] >> 62) + { + case 0: // byte + { + u8 val = WriteBufferFifo[WBWritePointer] & 0xFF; + if (WBAddr < ITCMSize) + { + *(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; + else BusWrite8(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + break; + } + case 1: // halfword + { + u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF; + if (WBAddr < ITCMSize) + { + *(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; + else BusWrite16(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + break; + } + case 2: // word + { + u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; + if (WBAddr < ITCMSize) + { + *(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; + else BusWrite32(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + WBAddr += 4; + break; + } + case 3: // address update + WBAddr = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; + break; + } + + WBWritePointer = (WBWritePointer + 1) & 0xF; + if (WBWritePointer == WBFillPointer) + { + WBWritePointer = 16; + WBFillPointer = 0; + break; + } + } +} + +void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr) +{ + WriteBufferCheck(); + + if (WBFillPointer == WBWritePointer) + { + //printf("forcedrainingwb %lli, %i %08X %i\n", WBCycles[WBWritePointer], WBWritePointer, WBAddr, WriteBufferFifo[WBWritePointer] >> 62); + if (NDS.ARM9Timestamp < WBCycles[WBWritePointer]) + { + NDS.ARM9Timestamp = WBCycles[WBWritePointer]; + DataCycles = 0; // checkme + } + + switch ((u64)WriteBufferFifo[WBWritePointer] >> 62) + { + case 0: // byte + { + u8 val = WriteBufferFifo[WBWritePointer] & 0xFF; + if (WBAddr < ITCMSize) + { + *(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; + else BusWrite8(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + break; + } + case 1: // halfword + { + u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF; + if (WBAddr < ITCMSize) + { + *(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; + else BusWrite16(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + break; + } + case 2: // word + { + u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; + if (WBAddr < ITCMSize) + { + *(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; + else BusWrite32(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + WBAddr += 4; + break; + } + case 3: // address update + WBAddr = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; + break; + } + + WBWritePointer = (WBWritePointer + 1) & 0xF; + if (WBWritePointer == WBFillPointer) + { + WBWritePointer = 16; + WBFillPointer = 0; + } + } + + //printf("fillingwb %lli %i %i %08X %i\n", NDS.ARM9Timestamp, WBWritePointer, WBFillPointer, val, flag); + if (WBWritePointer == 16) + { + WBCycles[WBFillPointer] = NDS.ARM9Timestamp + DataCycles + cycles; + WBWritePointer = 0; + } + else + { + WBCycles[WBFillPointer] = WBCycles[(WBFillPointer-1) & 0xF] + cycles; + } + WriteBufferFifo[WBFillPointer] = val | (u64)flag << 62; + storeaddr[WBFillPointer] = addr; + WBFillPointer = (WBFillPointer + 1) & 0xF; +} + +void ARMv5::WriteBufferDrain() +{ + if (WBWritePointer == 16) return; + + while (true) + { + //printf("fullydrainingwb %lli, %i %08X %i\n", WBCycles[WBWritePointer], WBWritePointer, WBAddr, WriteBufferFifo[WBWritePointer] >> 62); + if (NDS.ARM9Timestamp < WBCycles[WBWritePointer]) + { + NDS.ARM9Timestamp = WBCycles[WBWritePointer]; + DataCycles = 0; // checkme + } + + switch (WriteBufferFifo[WBWritePointer] >> 62) + { + case 0: // byte + { + u8 val = WriteBufferFifo[WBWritePointer] & 0xFF; + if (WBAddr < ITCMSize) + { + *(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; + else BusWrite8(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + break; + } + case 1: // halfword + { + u16 val = WriteBufferFifo[WBWritePointer] & 0xFFFF; + if (WBAddr < ITCMSize) + { + *(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; + else BusWrite16(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + break; + } + case 2: // word + { + u32 val = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; + if (WBAddr < ITCMSize) + { + *(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); + } + else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; + else BusWrite32(storeaddr[WBWritePointer], val); + if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); + WBAddr += 4; + break; + } + case 3: // address update + WBAddr = WriteBufferFifo[WBWritePointer] & 0xFFFFFFFF; + break; + } + + WBWritePointer = (WBWritePointer + 1) & 0xF; + if (WBWritePointer == WBFillPointer) + { + WBWritePointer = 16; + WBFillPointer = 0; + break; + } + } + //printf("wbdrained\n"); +} void ARMv5::CP15Write(u32 id, u32 val) { @@ -788,6 +1005,9 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch) return 0; } + if ((PU_Map[addr>>12] & 0x30)) + WriteBufferDrain(); + if (addr < ITCMSize) { CodeCycles = 1; @@ -837,6 +1057,9 @@ bool ARMv5::DataRead8(u32 addr, u32* val) DataCycles = 1; return false; } + + if ((PU_Map[addr>>12] & 0x30)) + WriteBufferDrain(); if (addr < ITCMSize) { @@ -882,6 +1105,8 @@ bool ARMv5::DataRead16(u32 addr, u32* val) } addr &= ~1; + if ((PU_Map[addr>>CP15_MAP_ENTRYSIZE_LOG2] & (CP15_MAP_DCACHEWRITEBACK | CP15_MAP_DCACHEABLE))) + WriteBufferDrain(); if (addr < ITCMSize) { @@ -928,6 +1153,9 @@ bool ARMv5::DataRead32(u32 addr, u32* val) addr &= ~3; + if ((PU_Map[addr>>12] & 0x30)) + WriteBufferDrain(); + if (addr < ITCMSize) { DataCycles = 1; @@ -972,6 +1200,9 @@ bool ARMv5::DataRead32S(u32 addr, u32* val) addr &= ~3; + if ((PU_Map[addr>>12] & 0x30)) + WriteBufferDrain(); + if (addr < ITCMSize) { DataCycles += 1; @@ -1016,37 +1247,46 @@ bool ARMv5::DataWrite8(u32 addr, u8 val) return false; } - if (addr < ITCMSize) + if (!(PU_Map[addr>>12] & (0x30))) { - DataCycles = 1; - ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; - DataRegion = Mem9_ITCM; - *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; - NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); - return true; - } - if ((addr & DTCMMask) == DTCMBase) - { - DataCycles = 1; - DataRegion = Mem9_DTCM; - *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; - return true; - } - - NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<(addr); + return true; + } + if ((addr & DTCMMask) == DTCMBase) + { + DataCycles = 1; + DataRegion = Mem9_DTCM; + *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; + return true; + } - DataCycles = MemTimings[addr >> 12][1]; + NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<> 12][1]; - if ((addr >> 24) == 0x02) - { - if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp; - DataRegion = Mem9_MainRAM; - MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles; - DataCycles -= (2<> 24) == 0x02) + { + if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp; + DataRegion = Mem9_MainRAM; + MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles; + DataCycles -= (2<>14]; + + BusWrite8(addr, val); + } + else + { + DataCycles = 1; + WriteBufferWrite(addr, 3, 1); + WriteBufferWrite(val, 0, MemTimings[addr >> 12][1], addr); } - else DataRegion = NDS.ARM9Regions[addr>>14]; - - BusWrite8(addr, val); return true; } @@ -1063,37 +1303,47 @@ bool ARMv5::DataWrite16(u32 addr, u16 val) addr &= ~1; - if (addr < ITCMSize) - { - DataCycles = 1; - ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; - DataRegion = Mem9_ITCM; - *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; - NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); - return true; - } - if ((addr & DTCMMask) == DTCMBase) - { - DataCycles = 1; - DataRegion = Mem9_DTCM; - *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; - return true; - } - NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<>12] & 0x30)) + { + if (addr < ITCMSize) + { + DataCycles = 1; + ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; + DataRegion = Mem9_ITCM; + *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); + return true; + } + if ((addr & DTCMMask) == DTCMBase) + { + DataCycles = 1; + DataRegion = Mem9_DTCM; + *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; + return true; + } - DataCycles = MemTimings[addr >> 12][1]; + NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<> 12][1]; - if ((addr >> 24) == 0x02) - { - if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp; - DataRegion = Mem9_MainRAM; - MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles; - DataCycles -= (2<> 24) == 0x02) + { + if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp; + DataRegion = Mem9_MainRAM; + MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles; + DataCycles -= (2<>14]; + + BusWrite16(addr, val); + } + else + { + DataCycles = 1; + WriteBufferWrite(addr, 3, 1); + WriteBufferWrite(val, 1, MemTimings[addr >> 12][1], addr); } - else DataRegion = NDS.ARM9Regions[addr>>14]; - - BusWrite16(addr, val); return true; } @@ -1110,37 +1360,47 @@ bool ARMv5::DataWrite32(u32 addr, u32 val) addr &= ~3; - if (addr < ITCMSize) - { - DataCycles = 1; - ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; - DataRegion = Mem9_ITCM; - *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; - NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); - return true; - } - if ((addr & DTCMMask) == DTCMBase) - { - DataCycles = 1; - DataRegion = Mem9_DTCM; - *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; - return true; - } - NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<>12] & 0x30)) + { + if (addr < ITCMSize) + { + DataCycles = 1; + ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; + DataRegion = Mem9_ITCM; + *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); + return true; + } + if ((addr & DTCMMask) == DTCMBase) + { + DataCycles = 1; + DataRegion = Mem9_DTCM; + *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; + return true; + } - DataCycles = MemTimings[addr >> 12][2]; + NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<> 12][2]; - if ((addr >> 24) == 0x02) - { - if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp; - DataRegion = Mem9_MainRAM; - MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles; - DataCycles -= (2<> 24) == 0x02) + { + if (NDS.ARM9Timestamp < MainRAMTimestamp) NDS.ARM9Timestamp = MainRAMTimestamp; + DataRegion = Mem9_MainRAM; + MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles; + DataCycles -= (2<>14]; + + BusWrite32(addr, val); + } + else + { + DataCycles = 1; + WriteBufferWrite(addr, 3, 1); + WriteBufferWrite(val, 2, MemTimings[addr >> 12][2], addr); } - else DataRegion = NDS.ARM9Regions[addr>>14]; - - BusWrite32(addr, val); return true; } @@ -1156,38 +1416,46 @@ bool ARMv5::DataWrite32S(u32 addr, u32 val) addr &= ~3; - if (addr < ITCMSize) + + if (!(PU_Map[addr>>12] & 0x30)) + { + if (addr < ITCMSize) + { + DataCycles += 1; + ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; + DataRegion = Mem9_ITCM; + *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; + #ifdef JIT_ENABLED + NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); + #endif + return true; + } + if ((addr & DTCMMask) == DTCMBase) + { + DataCycles += 1; + DataRegion = Mem9_DTCM; + *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; + return true; + } + + NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<> 24) == 0x02) + { + if ((DataRegion != Mem9_MainRAM) && ((NDS.ARM9Timestamp + DataCycles) < MainRAMTimestamp)) NDS.ARM9Timestamp = MainRAMTimestamp - DataCycles; + MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles; + DataRegion = Mem9_MainRAM; + } + else DataRegion = NDS.ARM9Regions[addr>>14]; + + BusWrite32(addr, val); + DataCycles += MemTimings[addr >> 12][3]; + } + else { DataCycles += 1; - ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; - DataRegion = Mem9_ITCM; - *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; -#ifdef JIT_ENABLED - NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); -#endif - return true; + WriteBufferWrite(val, 2, MemTimings[addr >> 12][3], addr); } - if ((addr & DTCMMask) == DTCMBase) - { - DataCycles += 1; - DataRegion = Mem9_DTCM; - *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val; - return true; - } - - NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<> 24) == 0x02) - { - if ((DataRegion != Mem9_MainRAM) && ((NDS.ARM9Timestamp + DataCycles) < MainRAMTimestamp)) NDS.ARM9Timestamp = MainRAMTimestamp - DataCycles; - MainRAMTimestamp = NDS.ARM9Timestamp + DataCycles; - DataRegion = Mem9_MainRAM; - } - else DataRegion = NDS.ARM9Regions[addr>>14]; - - BusWrite32(addr, val); - DataCycles += MemTimings[addr >> 12][3]; return true; } From 9cf065e54f9555dfd919c6d92f0da946e26d7044 Mon Sep 17 00:00:00 2001 From: Jaklyy <102590697+Jaklyy@users.noreply.github.com> Date: Wed, 9 Oct 2024 17:37:25 -0400 Subject: [PATCH 2/3] idk --- src/CP15.cpp | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/src/CP15.cpp b/src/CP15.cpp index 613c1bd5..d085cf02 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -457,7 +457,6 @@ void ARMv5::WriteBufferCheck() } else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; else BusWrite8(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); break; } case 1: // halfword @@ -470,7 +469,6 @@ void ARMv5::WriteBufferCheck() } else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; else BusWrite16(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); break; } case 2: // word @@ -483,7 +481,6 @@ void ARMv5::WriteBufferCheck() } else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; else BusWrite32(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); WBAddr += 4; break; } @@ -527,7 +524,6 @@ void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr) } else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; else BusWrite8(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); break; } case 1: // halfword @@ -540,7 +536,6 @@ void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr) } else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; else BusWrite16(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); break; } case 2: // word @@ -553,7 +548,6 @@ void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr) } else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; else BusWrite32(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); WBAddr += 4; break; } @@ -610,7 +604,6 @@ void ARMv5::WriteBufferDrain() } else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; else BusWrite8(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); break; } case 1: // halfword @@ -623,7 +616,6 @@ void ARMv5::WriteBufferDrain() } else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; else BusWrite16(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); break; } case 2: // word @@ -636,7 +628,6 @@ void ARMv5::WriteBufferDrain() } else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; else BusWrite32(storeaddr[WBWritePointer], val); - if (WBAddr != storeaddr[WBWritePointer]) printf("ERROR!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"); WBAddr += 4; break; } @@ -1218,8 +1209,11 @@ bool ARMv5::DataRead32S(u32 addr, u32* val) *val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)]; return true; } - + NDS.ARM9Timestamp += DataCycles; + + if (!(addr & 0x3FF)) return DataRead32(addr, val); // bursts cannot cross a 1kb boundary + DataCycles = MemTimings[addr >> 12][3]; NDS.ARM9Timestamp = NDS.ARM9Timestamp + ((1<> 24) == 0x02) { if ((DataRegion != Mem9_MainRAM) && ((NDS.ARM9Timestamp + DataCycles) < MainRAMTimestamp)) NDS.ARM9Timestamp = MainRAMTimestamp - DataCycles; From 35c382acabac3084391b83e3be85db46b974e83f Mon Sep 17 00:00:00 2001 From: Jaklyy <102590697+Jaklyy@users.noreply.github.com> Date: Wed, 9 Oct 2024 17:51:00 -0400 Subject: [PATCH 3/3] jit --- src/CP15.cpp | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/src/CP15.cpp b/src/CP15.cpp index d085cf02..c49034af 100644 --- a/src/CP15.cpp +++ b/src/CP15.cpp @@ -453,7 +453,9 @@ void ARMv5::WriteBufferCheck() if (WBAddr < ITCMSize) { *(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; else BusWrite8(storeaddr[WBWritePointer], val); @@ -465,7 +467,9 @@ void ARMv5::WriteBufferCheck() if (WBAddr < ITCMSize) { *(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; else BusWrite16(storeaddr[WBWritePointer], val); @@ -477,7 +481,9 @@ void ARMv5::WriteBufferCheck() if (WBAddr < ITCMSize) { *(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; else BusWrite32(storeaddr[WBWritePointer], val); @@ -520,7 +526,9 @@ void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr) if (WBAddr < ITCMSize) { *(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; else BusWrite8(storeaddr[WBWritePointer], val); @@ -532,7 +540,9 @@ void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr) if (WBAddr < ITCMSize) { *(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; else BusWrite16(storeaddr[WBWritePointer], val); @@ -544,7 +554,9 @@ void ARMv5::WriteBufferWrite(u32 val, u8 flag, u8 cycles, u32 addr) if (WBAddr < ITCMSize) { *(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; else BusWrite32(storeaddr[WBWritePointer], val); @@ -600,7 +612,9 @@ void ARMv5::WriteBufferDrain() if (WBAddr < ITCMSize) { *(u8*)&ITCM[WBAddr & (ITCMPhysicalSize - 1)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u8*)&DTCM[WBAddr & (DTCMPhysicalSize - 1)] = val; else BusWrite8(storeaddr[WBWritePointer], val); @@ -612,7 +626,9 @@ void ARMv5::WriteBufferDrain() if (WBAddr < ITCMSize) { *(u16*)&ITCM[WBAddr & (ITCMPhysicalSize - 2)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u16*)&DTCM[WBAddr & (DTCMPhysicalSize - 2)] = val; else BusWrite16(storeaddr[WBWritePointer], val); @@ -624,7 +640,9 @@ void ARMv5::WriteBufferDrain() if (WBAddr < ITCMSize) { *(u32*)&ITCM[WBAddr & (ITCMPhysicalSize - 4)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(WBAddr); +#endif } else if ((WBAddr & DTCMMask) == DTCMBase) *(u32*)&DTCM[WBAddr & (DTCMPhysicalSize - 4)] = val; else BusWrite32(storeaddr[WBWritePointer], val); @@ -1096,7 +1114,7 @@ bool ARMv5::DataRead16(u32 addr, u32* val) } addr &= ~1; - if ((PU_Map[addr>>CP15_MAP_ENTRYSIZE_LOG2] & (CP15_MAP_DCACHEWRITEBACK | CP15_MAP_DCACHEABLE))) + if ((PU_Map[addr>>12] & 0x30)) WriteBufferDrain(); if (addr < ITCMSize) @@ -1249,7 +1267,9 @@ bool ARMv5::DataWrite8(u32 addr, u8 val) ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; DataRegion = Mem9_ITCM; *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); +#endif return true; } if ((addr & DTCMMask) == DTCMBase) @@ -1306,7 +1326,9 @@ bool ARMv5::DataWrite16(u32 addr, u16 val) ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; DataRegion = Mem9_ITCM; *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); +#endif return true; } if ((addr & DTCMMask) == DTCMBase) @@ -1363,7 +1385,9 @@ bool ARMv5::DataWrite32(u32 addr, u32 val) ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; DataRegion = Mem9_ITCM; *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); +#endif return true; } if ((addr & DTCMMask) == DTCMBase) @@ -1419,9 +1443,9 @@ bool ARMv5::DataWrite32S(u32 addr, u32 val) ITCMTimestamp = NDS.ARM9Timestamp + DataCycles; DataRegion = Mem9_ITCM; *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val; - #ifdef JIT_ENABLED +#ifdef JIT_ENABLED NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); - #endif +#endif return true; } if ((addr & DTCMMask) == DTCMBase)