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implement a main ram burst restart behavior

This commit is contained in:
Jaklyy 2024-12-15 06:34:36 -05:00
parent d912429d8c
commit 2247f17f4f
2 changed files with 18 additions and 15 deletions
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30
src/NDS.cpp
View File

@ -926,8 +926,9 @@ void NDS::MainRAMHandleARM9()
case MainRAMType::Fetch: case MainRAMType::Fetch:
{ {
u8 var = ARM9.MRTrack.Var; u8 var = ARM9.MRTrack.Var;
u32 addr = (var & MRCodeFetch) ? ARM9.FetchAddr[16] : ARM9.FetchAddr[ARM9.MRTrack.Progress];
if ((var & MRSequential) && A9WENTLAST) if ((var & MRSequential) && A9WENTLAST && !(MainRAMBork && ((addr & 0x1F) == 0)))
{ {
A9ContentionTS += 2; A9ContentionTS += 2;
MainRAMTimestamp += 2; MainRAMTimestamp += 2;
@ -936,7 +937,8 @@ void NDS::MainRAMHandleARM9()
else else
{ {
if (A9ContentionTS < MainRAMTimestamp) { A9ContentionTS = MainRAMTimestamp; if (A7PRIORITY) return; } if (A9ContentionTS < MainRAMTimestamp) { A9ContentionTS = MainRAMTimestamp; if (A7PRIORITY) return; }
MainRAMBork = !(var & MRWrite) && ((addr & 0x1F) >= 0x1A);
MainRAMTimestamp = A9ContentionTS + ((var & MR16) ? 8 : 9); // checkme: are these correct for 8bit? MainRAMTimestamp = A9ContentionTS + ((var & MR16) ? 8 : 9); // checkme: are these correct for 8bit?
if (var & MRWrite) A9ContentionTS += ((var & MR16) ? 5 : 6); // checkme: is this correct for 133mhz? if (var & MRWrite) A9ContentionTS += ((var & MR16) ? 5 : 6); // checkme: is this correct for 133mhz?
else else
@ -1069,10 +1071,10 @@ void NDS::MainRAMHandleARM9()
{ {
if (srcrgn == Mem9_MainRAM) if (srcrgn == Mem9_MainRAM)
{ {
if (burststart == 2 || A7WENTLAST || DMALastWasMainRAM || dma->SrcAddrInc <= 0 || ((A9ContentionTS - DMABurstStart) >= 242) || (DMABORK && ((dma->CurSrcAddr & 0x1F) == 0))) if (burststart == 2 || A7WENTLAST || DMALastWasMainRAM || dma->SrcAddrInc <= 0 || ((A9ContentionTS - DMABurstStart) >= 242) || (MainRAMBork && ((dma->CurSrcAddr & 0x1F) == 0)))
{ {
if (A9ContentionTS < MainRAMTimestamp) { A9ContentionTS = MainRAMTimestamp; if (A7PRIORITY) return; } if (A9ContentionTS < MainRAMTimestamp) { A9ContentionTS = MainRAMTimestamp; if (A7PRIORITY) return; }
DMABORK = ((dma->CurSrcAddr & 0x1F) >= 0x1A); MainRAMBork = ((dma->CurSrcAddr & 0x1F) >= 0x1A);
MainRAMTimestamp = A9ContentionTS + 9; MainRAMTimestamp = A9ContentionTS + 9;
A9ContentionTS += 6; A9ContentionTS += 6;
MainRAMLastAccess = A9LAST; MainRAMLastAccess = A9LAST;
@ -1173,10 +1175,10 @@ void NDS::MainRAMHandleARM9()
{ {
if (srcrgn == Mem9_MainRAM) if (srcrgn == Mem9_MainRAM)
{ {
if (burststart == 2 || A7WENTLAST || DMALastWasMainRAM || dma->SrcAddrInc <= 0 || ((A9ContentionTS - DMABurstStart) >= 242) || (DMABORK && ((dma->CurSrcAddr & 0x1F) == 0))) if (burststart == 2 || A7WENTLAST || DMALastWasMainRAM || dma->SrcAddrInc <= 0 || ((A9ContentionTS - DMABurstStart) >= 242) || (MainRAMBork && ((dma->CurSrcAddr & 0x1F) == 0)))
{ {
if (A9ContentionTS < MainRAMTimestamp) { A9ContentionTS = MainRAMTimestamp; if (A7PRIORITY) return; } if (A9ContentionTS < MainRAMTimestamp) { A9ContentionTS = MainRAMTimestamp; if (A7PRIORITY) return; }
DMABORK = ((dma->CurSrcAddr & 0x1F) >= 0x1A); MainRAMBork = ((dma->CurSrcAddr & 0x1F) >= 0x1A);
DMABurstStart = A9ContentionTS; DMABurstStart = A9ContentionTS;
MainRAMTimestamp = A9ContentionTS + 8; MainRAMTimestamp = A9ContentionTS + 8;
A9ContentionTS += 5; A9ContentionTS += 5;
@ -1366,8 +1368,9 @@ void NDS::MainRAMHandleARM7()
case MainRAMType::Fetch: case MainRAMType::Fetch:
{ {
u8 var = ARM7.MRTrack.Var; u8 var = ARM7.MRTrack.Var;
u32 addr = (var & MRCodeFetch) ? ARM7.FetchAddr[16] : ARM7.FetchAddr[ARM7.MRTrack.Progress];
if ((var & MRSequential) && A7WENTLAST) if ((var & MRSequential) && A7WENTLAST && !(MainRAMBork && ((addr & 0x1F) == 0)))
{ {
int cycles = ((var & MR32) ? 2 : 1); int cycles = ((var & MR32) ? 2 : 1);
MainRAMTimestamp += cycles; MainRAMTimestamp += cycles;
@ -1377,7 +1380,8 @@ void NDS::MainRAMHandleARM7()
else else
{ {
if (ARM7Timestamp < MainRAMTimestamp) { ARM7Timestamp = MainRAMTimestamp; if (A9PRIORITY) return; } if (ARM7Timestamp < MainRAMTimestamp) { ARM7Timestamp = MainRAMTimestamp; if (A9PRIORITY) return; }
MainRAMBork = !(var & MRWrite) && ((addr & 0x1F) >= 0x1A);
MainRAMTimestamp = ARM7Timestamp + ((var & MR16) ? 8 : 9); // checkme: are these correct for 8bit? MainRAMTimestamp = ARM7Timestamp + ((var & MR16) ? 8 : 9); // checkme: are these correct for 8bit?
if (var & MRWrite) ARM7Timestamp += ((var & MR16) ? 3 : 4); if (var & MRWrite) ARM7Timestamp += ((var & MR16) ? 3 : 4);
else ARM7Timestamp += ((var & MR16) ? 5 : 6); else ARM7Timestamp += ((var & MR16) ? 5 : 6);
@ -1386,13 +1390,11 @@ void NDS::MainRAMHandleARM7()
if (var & MRCodeFetch) if (var & MRCodeFetch)
{ {
u32 addr = ARM7.FetchAddr[16];
ARM7.RetVal = ((var & MR32) ? *(u32*)&MainRAM[addr&MainRAMMask] : *(u16*)&MainRAM[addr&MainRAMMask]); ARM7.RetVal = ((var & MR32) ? *(u32*)&MainRAM[addr&MainRAMMask] : *(u16*)&MainRAM[addr&MainRAMMask]);
} }
else else
{ {
u8 reg = ARM7.MRTrack.Progress; u8 reg = ARM7.MRTrack.Progress;
u32 addr = ARM7.FetchAddr[reg];
if (var & MRWrite) // write if (var & MRWrite) // write
{ {
u32 val = ARM7.STRVal[reg]; u32 val = ARM7.STRVal[reg];
@ -1426,10 +1428,10 @@ void NDS::MainRAMHandleARM7()
{ {
if (srcrgn == Mem7_MainRAM) if (srcrgn == Mem7_MainRAM)
{ {
if (burststart == 2 || A9WENTLAST || DMALastWasMainRAM || dma->SrcAddrInc <= 0 || ((ARM7Timestamp - DMABurstStart) >= 242) || (DMABORK && ((dma->CurSrcAddr & 0x1F) == 0))) if (burststart == 2 || A9WENTLAST || DMALastWasMainRAM || dma->SrcAddrInc <= 0 || ((ARM7Timestamp - DMABurstStart) >= 242) || (MainRAMBork && ((dma->CurSrcAddr & 0x1F) == 0)))
{ {
if (ARM7Timestamp < MainRAMTimestamp) { ARM7Timestamp = MainRAMTimestamp; if (A9PRIORITY) return; } if (ARM7Timestamp < MainRAMTimestamp) { ARM7Timestamp = MainRAMTimestamp; if (A9PRIORITY) return; }
DMABORK = ((dma->CurSrcAddr & 0x1F) >= 0x1A); MainRAMBork = ((dma->CurSrcAddr & 0x1F) >= 0x1A);
DMABurstStart = ARM7Timestamp; DMABurstStart = ARM7Timestamp;
MainRAMTimestamp = ARM7Timestamp + 9; MainRAMTimestamp = ARM7Timestamp + 9;
ARM7Timestamp += 6; ARM7Timestamp += 6;
@ -1528,10 +1530,10 @@ void NDS::MainRAMHandleARM7()
{ {
if (srcrgn == Mem7_MainRAM) if (srcrgn == Mem7_MainRAM)
{ {
if (burststart == 2 || A9WENTLAST || DMALastWasMainRAM || dma->SrcAddrInc <= 0 || ((ARM7Timestamp - DMABurstStart) >= 242) || (DMABORK && ((dma->CurSrcAddr & 0x1F) == 0))) if (burststart == 2 || A9WENTLAST || DMALastWasMainRAM || dma->SrcAddrInc <= 0 || ((ARM7Timestamp - DMABurstStart) >= 242) || (MainRAMBork && ((dma->CurSrcAddr & 0x1F) == 0)))
{ {
if (ARM7Timestamp < MainRAMTimestamp) { ARM7Timestamp = MainRAMTimestamp; if (A9PRIORITY) return; } if (ARM7Timestamp < MainRAMTimestamp) { ARM7Timestamp = MainRAMTimestamp; if (A9PRIORITY) return; }
DMABORK = ((dma->CurSrcAddr & 0x1F) >= 0x1A); MainRAMBork = ((dma->CurSrcAddr & 0x1F) >= 0x1A);
DMABurstStart = ARM7Timestamp; DMABurstStart = ARM7Timestamp;
MainRAMTimestamp = ARM7Timestamp + 8; MainRAMTimestamp = ARM7Timestamp + 8;
ARM7Timestamp += 5; ARM7Timestamp += 5;

3
src/NDS.h
View File

@ -276,7 +276,8 @@ public: // TODO: Encapsulate the rest of these members
alignas(u32) u8 ROMSeed0[2*8]; alignas(u32) u8 ROMSeed0[2*8];
alignas(u32) u8 ROMSeed1[2*8]; alignas(u32) u8 ROMSeed1[2*8];
u32 DMAReadHold; bool DMABORK; u32 DMAReadHold;
bool MainRAMBork; // if a main ram read burst starts in the last 6 bytes of a 32 byte block, and then crosses the 32 byte boundary, the burst forcibly restarts
bool MainRAMLastAccess; // 0 == ARM9 | 1 == ARM7 bool MainRAMLastAccess; // 0 == ARM9 | 1 == ARM7
bool DMALastWasMainRAM; bool DMALastWasMainRAM;