From 1e4086e1b631e6121261c909f3aa1b7b342d7c89 Mon Sep 17 00:00:00 2001 From: StapleButter Date: Sat, 3 Dec 2016 17:58:24 +0100 Subject: [PATCH] moar instructions and shit implemented --- ARM.cpp | 27 +- ARMInterpreter_ALU.cpp | 134 ++++++++- ARMInterpreter_ALU.h | 13 + ARMInterpreter_Branch.cpp | 8 + ARMInterpreter_Branch.h | 1 + ARMInterpreter_LoadStore.cpp | 177 ++++++++++++ ARMInterpreter_LoadStore.h | 11 + ARM_InstrTable.h | 532 +++++++++++++++++------------------ NDS.cpp | 6 +- melonDS.depend | 19 +- 10 files changed, 648 insertions(+), 280 deletions(-) diff --git a/ARM.cpp b/ARM.cpp index 6ca6ff1b..7d4beae9 100644 --- a/ARM.cpp +++ b/ARM.cpp @@ -73,7 +73,32 @@ void ARM::JumpTo(u32 addr) void ARM::RestoreCPSR() { - printf("TODO: restore CPSR\n"); + switch (CPSR & 0x1F) + { + case 0x11: + CPSR = R_FIQ[8]; + break; + + case 0x12: + CPSR = R_IRQ[2]; + break; + + case 0x13: + CPSR = R_SVC[2]; + break; + + case 0x17: + CPSR = R_ABT[2]; + break; + + case 0x1B: + CPSR = R_UND[2]; + break; + + default: + printf("!! attempt to restore CPSR under bad mode %02X\n", CPSR&0x1F); + break; + } } void ARM::UpdateMode(u32 oldmode, u32 newmode) diff --git a/ARMInterpreter_ALU.cpp b/ARMInterpreter_ALU.cpp index 46f8107f..eae671ff 100644 --- a/ARMInterpreter_ALU.cpp +++ b/ARMInterpreter_ALU.cpp @@ -749,7 +749,57 @@ s32 T_ASR_IMM(ARM* cpu) return C_S(1); } -// +s32 T_ADD_REG_(ARM* cpu) +{ + u32 a = cpu->R[(cpu->CurInstr >> 3) & 0x7]; + u32 b = cpu->R[(cpu->CurInstr >> 6) & 0x7]; + u32 res = a + b; + cpu->R[cpu->CurInstr & 0x7] = res; + cpu->SetNZCV(res & 0x80000000, + !res, + CARRY_ADD(a, b), + OVERFLOW_ADD(a, b, res)); + return C_S(1); +} + +s32 T_SUB_REG_(ARM* cpu) +{ + u32 a = cpu->R[(cpu->CurInstr >> 3) & 0x7]; + u32 b = cpu->R[(cpu->CurInstr >> 6) & 0x7]; + u32 res = a - b; + cpu->R[cpu->CurInstr & 0x7] = res; + cpu->SetNZCV(res & 0x80000000, + !res, + CARRY_SUB(a, b), + OVERFLOW_SUB(a, b, res)); + return C_S(1); +} + +s32 T_ADD_IMM_(ARM* cpu) +{ + u32 a = cpu->R[(cpu->CurInstr >> 3) & 0x7]; + u32 b = (cpu->CurInstr >> 6) & 0x7; + u32 res = a + b; + cpu->R[cpu->CurInstr & 0x7] = res; + cpu->SetNZCV(res & 0x80000000, + !res, + CARRY_ADD(a, b), + OVERFLOW_ADD(a, b, res)); + return C_S(1); +} + +s32 T_SUB_IMM_(ARM* cpu) +{ + u32 a = cpu->R[(cpu->CurInstr >> 3) & 0x7]; + u32 b = (cpu->CurInstr >> 6) & 0x7; + u32 res = a - b; + cpu->R[cpu->CurInstr & 0x7] = res; + cpu->SetNZCV(res & 0x80000000, + !res, + CARRY_SUB(a, b), + OVERFLOW_SUB(a, b, res)); + return C_S(1); +} s32 T_MOV_IMM(ARM* cpu) { @@ -997,4 +1047,86 @@ s32 T_MVN_REG(ARM* cpu) } +s32 T_ADD_HIREG(ARM* cpu) +{ + u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8); + u32 rs = (cpu->CurInstr >> 3) & 0xF; + + u32 a = cpu->R[rd]; + u32 b = cpu->R[rs]; + + if (rd == 15) + { + cpu->JumpTo(a + b); + return C_S(2) + C_N(1); + } + else + { + cpu->R[rd] = a + b; + return C_S(1); + } +} + +s32 T_CMP_HIREG(ARM* cpu) +{ + u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8); + u32 rs = (cpu->CurInstr >> 3) & 0xF; + + u32 a = cpu->R[rd]; + u32 b = cpu->R[rs]; + u32 res = a - b; + + cpu->SetNZCV(res & 0x80000000, + !res, + CARRY_SUB(a, b), + OVERFLOW_SUB(a, b, res)); + return C_S(1); +} + +s32 T_MOV_HIREG(ARM* cpu) +{ + u32 rd = (cpu->CurInstr & 0x7) | ((cpu->CurInstr >> 4) & 0x8); + u32 rs = (cpu->CurInstr >> 3) & 0xF; + + if (rd == 15) + { + cpu->JumpTo(cpu->R[rs]); + return C_S(2) + C_N(1); + } + else + { + cpu->R[rd] = cpu->R[rs]; + return C_S(1); + } +} + + +s32 T_ADD_PCREL(ARM* cpu) +{ + u32 val = cpu->R[15] = ~2; + val += ((cpu->CurInstr & 0xFF) << 2); + cpu->R[(cpu->CurInstr >> 8) & 0x7] = val; + return C_S(1); +} + +s32 T_ADD_SPREL(ARM* cpu) +{ + u32 val = cpu->R[13]; + val += ((cpu->CurInstr & 0xFF) << 2); + cpu->R[(cpu->CurInstr >> 8) & 0x7] = val; + return C_S(1); +} + +s32 T_ADD_SP(ARM* cpu) +{ + u32 val = cpu->R[13]; + if (cpu->CurInstr & (1<<7)) + val -= ((cpu->CurInstr & 0x7F) << 2); + else + val += ((cpu->CurInstr & 0x7F) << 2); + cpu->R[13] = val; + return C_S(1); +} + + } diff --git a/ARMInterpreter_ALU.h b/ARMInterpreter_ALU.h index 38872a83..d1195c37 100644 --- a/ARMInterpreter_ALU.h +++ b/ARMInterpreter_ALU.h @@ -60,6 +60,11 @@ s32 T_LSL_IMM(ARM* cpu); s32 T_LSR_IMM(ARM* cpu); s32 T_ASR_IMM(ARM* cpu); +s32 T_ADD_REG_(ARM* cpu); +s32 T_SUB_REG_(ARM* cpu); +s32 T_ADD_IMM_(ARM* cpu); +s32 T_SUB_IMM_(ARM* cpu); + s32 T_MOV_IMM(ARM* cpu); s32 T_CMP_IMM(ARM* cpu); s32 T_ADD_IMM(ARM* cpu); @@ -82,6 +87,14 @@ s32 T_MUL_REG(ARM* cpu); s32 T_BIC_REG(ARM* cpu); s32 T_MVN_REG(ARM* cpu); +s32 T_ADD_HIREG(ARM* cpu); +s32 T_CMP_HIREG(ARM* cpu); +s32 T_MOV_HIREG(ARM* cpu); + +s32 T_ADD_PCREL(ARM* cpu); +s32 T_ADD_SPREL(ARM* cpu); +s32 T_ADD_SP(ARM* cpu); + } #endif diff --git a/ARMInterpreter_Branch.cpp b/ARMInterpreter_Branch.cpp index 879b64fa..354dad36 100644 --- a/ARMInterpreter_Branch.cpp +++ b/ARMInterpreter_Branch.cpp @@ -85,6 +85,14 @@ s32 T_BLX_REG(ARM* cpu) return C_S(2) + C_N(1); } +s32 T_B(ARM* cpu) +{ + s32 offset = (s32)((cpu->CurInstr & 0x7FF) << 21) >> 20; + cpu->JumpTo(cpu->R[15] + offset + 1); + + return C_S(2) + C_N(1); +} + s32 T_BL_LONG_1(ARM* cpu) { s32 offset = (s32)((cpu->CurInstr & 0x7FF) << 21) >> 9; diff --git a/ARMInterpreter_Branch.h b/ARMInterpreter_Branch.h index eb60b82d..34192869 100644 --- a/ARMInterpreter_Branch.h +++ b/ARMInterpreter_Branch.h @@ -13,6 +13,7 @@ s32 A_BLX_REG(ARM* cpu); s32 T_BCOND(ARM* cpu); s32 T_BX(ARM* cpu); s32 T_BLX_REG(ARM* cpu); +s32 T_B(ARM* cpu); s32 T_BL_LONG_1(ARM* cpu); s32 T_BL_LONG_2(ARM* cpu); diff --git a/ARMInterpreter_LoadStore.cpp b/ARMInterpreter_LoadStore.cpp index 9e69f773..583f175d 100644 --- a/ARMInterpreter_LoadStore.cpp +++ b/ARMInterpreter_LoadStore.cpp @@ -1,3 +1,4 @@ +#include #include "ARM.h" @@ -309,6 +310,126 @@ A_IMPLEMENT_HD_LDRSTR(LDRSH) +s32 A_LDM(ARM* cpu) +{ + u32 base = cpu->R[(cpu->CurInstr >> 16) & 0xF]; + u32 preinc = (cpu->CurInstr & (1<<24)); + + if (!(cpu->CurInstr & (1<<23))) + { + for (int i = 0; i < 16; i++) + { + if (cpu->CurInstr & (1<CurInstr & (1<<21)) + { + cpu->R[(cpu->CurInstr >> 16) & 0xF] = base; + if (cpu->CurInstr & (1 << ((cpu->CurInstr >> 16) & 0xF))) + printf("!! BAD LDM\n"); + } + + preinc = !preinc; + } + + s32 cycles = C_N(1) + C_I(1); + + if ((cpu->CurInstr & (1<<22)) && !(cpu->CurInstr & (1<<15))) + cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10); + + for (int i = 0; i < 15; i++) + { + if (cpu->CurInstr & (1<R[i] = cpu->Read32(base); + cycles += C_S(1) + cpu->MemWaitstate(3, base); + if (!preinc) base += 4; + } + } + + if (cpu->CurInstr & (1<<15)) + { + if (preinc) base += 4; + u32 pc = cpu->Read32(base); + cycles += C_S(2) + C_N(1) + cpu->MemWaitstate(3, base); + if (!preinc) base += 4; + + if (cpu->Num == 1) + pc &= ~0x1; + + cpu->JumpTo(pc); + if (cpu->CurInstr & (1<<22)) cpu->RestoreCPSR(); + } + + if ((cpu->CurInstr & (1<<22)) && !(cpu->CurInstr & (1<<15))) + cpu->UpdateMode((cpu->CPSR&~0x1F)|0x10, cpu->CPSR); + + if ((cpu->CurInstr & (1<<23)) && (cpu->CurInstr & (1<<21))) + { + cpu->R[(cpu->CurInstr >> 16) & 0xF] = base; + if (cpu->CurInstr & (1 << ((cpu->CurInstr >> 16) & 0xF))) + printf("!! BAD LDM\n"); + } + + return cycles; +} + +s32 A_STM(ARM* cpu) +{ + u32 base = cpu->R[(cpu->CurInstr >> 16) & 0xF]; + u32 preinc = (cpu->CurInstr & (1<<24)); + + if (!(cpu->CurInstr & (1<<23))) + { + for (int i = 0; i < 16; i++) + { + if (cpu->CurInstr & (1<CurInstr & (1<<21)) + { + cpu->R[(cpu->CurInstr >> 16) & 0xF] = base; + if (cpu->CurInstr & (1 << ((cpu->CurInstr >> 16) & 0xF))) + printf("!! BAD STM\n"); + } + + preinc = !preinc; + } + + s32 cycles = C_N(1) + C_I(1); + + if (cpu->CurInstr & (1<<22)) + cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10); + + for (int i = 0; i < 16; i++) + { + if (cpu->CurInstr & (1<Write32(base, cpu->R[i]); + cycles += C_S(1) + cpu->MemWaitstate(3, base); + if (!preinc) base += 4; + } + } + + if (cpu->CurInstr & (1<<22)) + cpu->UpdateMode((cpu->CPSR&~0x1F)|0x10, cpu->CPSR); + + if ((cpu->CurInstr & (1<<23)) && (cpu->CurInstr & (1<<21))) + { + cpu->R[(cpu->CurInstr >> 16) & 0xF] = base; + if (cpu->CurInstr & (1 << ((cpu->CurInstr >> 16) & 0xF))) + printf("!! BAD STM\n"); + } + + return cycles; +} + + + // ---- THUMB ----------------------- @@ -356,6 +477,43 @@ s32 T_LDRB_REG(ARM* cpu) } +s32 T_STR_IMM(ARM* cpu) +{ + u32 offset = (cpu->CurInstr >> 4) & 0x7C; + offset += cpu->R[(cpu->CurInstr >> 3) & 0x7]; + + cpu->Write32(offset, cpu->R[cpu->CurInstr & 0x7]); + return C_N(2) + cpu->MemWaitstate(3, offset); +} + +s32 T_LDR_IMM(ARM* cpu) +{ + u32 offset = (cpu->CurInstr >> 4) & 0x7C; + offset += cpu->R[(cpu->CurInstr >> 3) & 0x7]; + + cpu->R[cpu->CurInstr & 0x7] = cpu->Read32(offset); + return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset); +} + +s32 T_STRB_IMM(ARM* cpu) +{ + u32 offset = (cpu->CurInstr >> 6) & 0x1F; + offset += cpu->R[(cpu->CurInstr >> 3) & 0x7]; + + cpu->Write8(offset, cpu->R[cpu->CurInstr & 0x7]); + return C_N(2) + cpu->MemWaitstate(3, offset); +} + +s32 T_LDRB_IMM(ARM* cpu) +{ + u32 offset = (cpu->CurInstr >> 6) & 0x1F; + offset += cpu->R[(cpu->CurInstr >> 3) & 0x7]; + + cpu->R[cpu->CurInstr & 0x7] = cpu->Read8(offset); + return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset); +} + + s32 T_STRH_IMM(ARM* cpu) { u32 offset = (cpu->CurInstr >> 5) & 0x3E; @@ -375,6 +533,25 @@ s32 T_LDRH_IMM(ARM* cpu) } +s32 T_STR_SPREL(ARM* cpu) +{ + u32 offset = (cpu->CurInstr << 2) & 0x3FC; + offset += cpu->R[13]; + + cpu->Write32(offset, cpu->R[(cpu->CurInstr >> 8) & 0x7]); + return C_N(2) + cpu->MemWaitstate(3, offset); +} + +s32 T_LDR_SPREL(ARM* cpu) +{ + u32 offset = (cpu->CurInstr << 2) & 0x3FC; + offset += cpu->R[13]; + + cpu->R[(cpu->CurInstr >> 8) & 0x7] = cpu->Read32(offset); + return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset); +} + + s32 T_PUSH(ARM* cpu) { int nregs = 0; diff --git a/ARMInterpreter_LoadStore.h b/ARMInterpreter_LoadStore.h index 1b7aae47..61b1a39f 100644 --- a/ARMInterpreter_LoadStore.h +++ b/ARMInterpreter_LoadStore.h @@ -37,6 +37,9 @@ A_PROTO_HD_LDRSTR(LDRH) A_PROTO_HD_LDRSTR(LDRSB) A_PROTO_HD_LDRSTR(LDRSH) +s32 A_LDM(ARM* cpu); +s32 A_STM(ARM* cpu); + s32 T_LDR_PCREL(ARM* cpu); @@ -45,9 +48,17 @@ s32 T_STRB_REG(ARM* cpu); s32 T_LDR_REG(ARM* cpu); s32 T_LDRB_REG(ARM* cpu); +s32 T_STR_IMM(ARM* cpu); +s32 T_LDR_IMM(ARM* cpu); +s32 T_STRB_IMM(ARM* cpu); +s32 T_LDRB_IMM(ARM* cpu); + s32 T_STRH_IMM(ARM* cpu); s32 T_LDRH_IMM(ARM* cpu); +s32 T_STR_SPREL(ARM* cpu); +s32 T_LDR_SPREL(ARM* cpu); + s32 T_PUSH(ARM* cpu); s32 T_POP(ARM* cpu); diff --git a/ARM_InstrTable.h b/ARM_InstrTable.h index 9180a1d4..78dd18c2 100644 --- a/ARM_InstrTable.h +++ b/ARM_InstrTable.h @@ -4,56 +4,56 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) = // 0000 0000 0000 A_AND_REG_LSL_IMM, A_AND_REG_LSL_REG, A_AND_REG_LSR_IMM, A_AND_REG_LSR_REG, A_AND_REG_ASR_IMM, A_AND_REG_ASR_REG, A_AND_REG_ROR_IMM, A_AND_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_STRH_POST_REG, - A_UNK, A_LDRD_POST_REG, A_UNK, A_STRD_POST_REG, + A_AND_REG_LSL_IMM, A_UNK, A_AND_REG_LSR_IMM, A_STRH_POST_REG, + A_AND_REG_ASR_IMM, A_LDRD_POST_REG, A_AND_REG_ROR_IMM, A_STRD_POST_REG, // 0000 0001 0000 A_AND_REG_LSL_IMM_S, A_AND_REG_LSL_REG_S, A_AND_REG_LSR_IMM_S, A_AND_REG_LSR_REG_S, A_AND_REG_ASR_IMM_S, A_AND_REG_ASR_REG_S, A_AND_REG_ROR_IMM_S, A_AND_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_LDRH_POST_REG, - A_UNK, A_LDRSB_POST_REG, A_UNK, A_LDRSH_POST_REG, + A_AND_REG_LSL_IMM_S, A_UNK, A_AND_REG_LSR_IMM_S, A_LDRH_POST_REG, + A_AND_REG_ASR_IMM_S, A_LDRSB_POST_REG, A_AND_REG_ROR_IMM_S, A_LDRSH_POST_REG, // 0000 0010 0000 A_EOR_REG_LSL_IMM, A_EOR_REG_LSL_REG, A_EOR_REG_LSR_IMM, A_EOR_REG_LSR_REG, A_EOR_REG_ASR_IMM, A_EOR_REG_ASR_REG, A_EOR_REG_ROR_IMM, A_EOR_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_EOR_REG_LSL_IMM, A_UNK, A_EOR_REG_LSR_IMM, A_UNK, + A_EOR_REG_ASR_IMM, A_UNK, A_EOR_REG_ROR_IMM, A_UNK, // 0000 0011 0000 A_EOR_REG_LSL_IMM_S, A_EOR_REG_LSL_REG_S, A_EOR_REG_LSR_IMM_S, A_EOR_REG_LSR_REG_S, A_EOR_REG_ASR_IMM_S, A_EOR_REG_ASR_REG_S, A_EOR_REG_ROR_IMM_S, A_EOR_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_EOR_REG_LSL_IMM_S, A_UNK, A_EOR_REG_ROR_IMM_S, A_UNK, + A_EOR_REG_ASR_IMM_S, A_UNK, A_EOR_REG_ROR_IMM_S, A_UNK, // 0000 0100 0000 A_SUB_REG_LSL_IMM, A_SUB_REG_LSL_REG, A_SUB_REG_LSR_IMM, A_SUB_REG_LSR_REG, A_SUB_REG_ASR_IMM, A_SUB_REG_ASR_REG, A_SUB_REG_ROR_IMM, A_SUB_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_STRH_POST_IMM, - A_UNK, A_LDRD_POST_IMM, A_UNK, A_STRD_POST_IMM, + A_SUB_REG_LSL_IMM, A_UNK, A_SUB_REG_LSR_IMM, A_STRH_POST_IMM, + A_SUB_REG_ASR_IMM, A_LDRD_POST_IMM, A_SUB_REG_ROR_IMM, A_STRD_POST_IMM, // 0000 0101 0000 A_SUB_REG_LSL_IMM_S, A_SUB_REG_LSL_REG_S, A_SUB_REG_LSR_IMM_S, A_SUB_REG_LSR_REG_S, A_SUB_REG_ASR_IMM_S, A_SUB_REG_ASR_REG_S, A_SUB_REG_ROR_IMM_S, A_SUB_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_LDRH_POST_IMM, - A_UNK, A_LDRSB_POST_IMM, A_UNK, A_LDRSH_POST_IMM, + A_SUB_REG_LSL_IMM_S, A_UNK, A_SUB_REG_LSR_IMM_S, A_LDRH_POST_IMM, + A_SUB_REG_ASR_IMM_S, A_LDRSB_POST_IMM, A_SUB_REG_ROR_IMM_S, A_LDRSH_POST_IMM, // 0000 0110 0000 A_RSB_REG_LSL_IMM, A_RSB_REG_LSL_REG, A_RSB_REG_LSR_IMM, A_RSB_REG_LSR_REG, A_RSB_REG_ASR_IMM, A_RSB_REG_ASR_REG, A_RSB_REG_ROR_IMM, A_RSB_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_RSB_REG_LSL_IMM, A_UNK, A_RSB_REG_LSR_IMM, A_UNK, + A_RSB_REG_ASR_IMM, A_UNK, A_RSB_REG_ROR_IMM, A_UNK, // 0000 0111 0000 A_RSB_REG_LSL_IMM_S, A_RSB_REG_LSL_REG_S, A_RSB_REG_LSR_IMM_S, A_RSB_REG_LSR_REG_S, A_RSB_REG_ASR_IMM_S, A_RSB_REG_ASR_REG_S, A_RSB_REG_ROR_IMM_S, A_RSB_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_RSB_REG_LSL_IMM_S, A_UNK, A_RSB_REG_LSR_IMM_S, A_UNK, + A_RSB_REG_ASR_IMM_S, A_UNK, A_RSB_REG_ROR_IMM_S, A_UNK, // 0000 1000 0000 A_ADD_REG_LSL_IMM, A_ADD_REG_LSL_REG, A_ADD_REG_LSR_IMM, A_ADD_REG_LSR_REG, A_ADD_REG_ASR_IMM, A_ADD_REG_ASR_REG, A_ADD_REG_ROR_IMM, A_ADD_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_STRH_POST_REG, - A_UNK, A_LDRD_POST_REG, A_UNK, A_STRD_POST_REG, + A_ADD_REG_LSL_IMM, A_UNK, A_ADD_REG_LSR_IMM, A_STRH_POST_REG, + A_ADD_REG_ASR_IMM, A_LDRD_POST_REG, A_ADD_REG_ROR_IMM, A_STRD_POST_REG, // 0000 1001 0000 A_ADD_REG_LSL_IMM_S, A_ADD_REG_LSL_REG_S, A_ADD_REG_LSR_IMM_S, A_ADD_REG_LSR_REG_S, @@ -64,38 +64,38 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) = // 0000 1010 0000 A_ADC_REG_LSL_IMM, A_ADC_REG_LSL_REG, A_ADC_REG_LSR_IMM, A_ADC_REG_LSR_REG, A_ADC_REG_ASR_IMM, A_ADC_REG_ASR_REG, A_ADC_REG_ROR_IMM, A_ADC_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_ADC_REG_LSL_IMM, A_UNK, A_ADC_REG_LSR_IMM, A_UNK, + A_ADC_REG_ASR_IMM, A_UNK, A_ADC_REG_ROR_IMM, A_UNK, // 0000 1011 0000 A_ADC_REG_LSL_IMM_S, A_ADC_REG_LSL_REG_S, A_ADC_REG_LSR_IMM_S, A_ADC_REG_LSR_REG_S, A_ADC_REG_ASR_IMM_S, A_ADC_REG_ASR_REG_S, A_ADC_REG_ROR_IMM_S, A_ADC_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_ADC_REG_LSL_IMM_S, A_UNK, A_ADC_REG_LSR_IMM_S, A_UNK, + A_ADC_REG_ASR_IMM_S, A_UNK, A_ADC_REG_ROR_IMM_S, A_UNK, // 0000 1100 0000 A_SBC_REG_LSL_IMM, A_SBC_REG_LSL_REG, A_SBC_REG_LSR_IMM, A_SBC_REG_LSR_REG, A_SBC_REG_ASR_IMM, A_SBC_REG_ASR_REG, A_SBC_REG_ROR_IMM, A_SBC_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_STRH_POST_IMM, - A_UNK, A_LDRD_POST_IMM, A_UNK, A_STRD_POST_IMM, + A_SBC_REG_LSL_IMM, A_UNK, A_SBC_REG_LSR_IMM, A_STRH_POST_IMM, + A_SBC_REG_ASR_IMM, A_LDRD_POST_IMM, A_SBC_REG_ROR_IMM, A_STRD_POST_IMM, // 0000 1101 0000 A_SBC_REG_LSL_IMM_S, A_SBC_REG_LSL_REG_S, A_SBC_REG_LSR_IMM_S, A_SBC_REG_LSR_REG_S, A_SBC_REG_ASR_IMM_S, A_SBC_REG_ASR_REG_S, A_SBC_REG_ROR_IMM_S, A_SBC_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_LDRH_POST_IMM, - A_UNK, A_LDRSB_POST_IMM, A_UNK, A_LDRSH_POST_IMM, + A_SBC_REG_LSL_IMM_S, A_UNK, A_SBC_REG_LSR_IMM_S, A_LDRH_POST_IMM, + A_SBC_REG_ASR_IMM_S, A_LDRSB_POST_IMM, A_SBC_REG_ROR_IMM_S, A_LDRSH_POST_IMM, // 0000 1110 0000 A_RSC_REG_LSL_IMM, A_RSC_REG_LSL_REG, A_RSC_REG_LSR_IMM, A_RSC_REG_LSR_REG, A_RSC_REG_ASR_IMM, A_RSC_REG_ASR_REG, A_RSC_REG_ROR_IMM, A_RSC_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_RSC_REG_LSL_IMM, A_UNK, A_RSC_REG_LSR_IMM, A_UNK, + A_RSC_REG_ASR_IMM, A_UNK, A_RSC_REG_ROR_IMM, A_UNK, // 0000 1111 0000 A_RSC_REG_LSL_IMM_S, A_RSC_REG_LSL_REG_S, A_RSC_REG_LSR_IMM_S, A_RSC_REG_LSR_REG_S, A_RSC_REG_ASR_IMM_S, A_RSC_REG_ASR_REG_S, A_RSC_REG_ROR_IMM_S, A_RSC_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_RSC_REG_LSL_IMM_S, A_UNK, A_RSC_REG_LSR_IMM_S, A_UNK, + A_RSC_REG_ASR_IMM_S, A_UNK, A_RSC_REG_ROR_IMM_S, A_UNK, @@ -108,8 +108,8 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) = // 0001 0001 0000 A_TST_REG_LSL_IMM, A_TST_REG_LSL_REG, A_TST_REG_LSR_IMM, A_TST_REG_LSR_REG, A_TST_REG_ASR_IMM, A_TST_REG_ASR_REG, A_TST_REG_ROR_IMM, A_TST_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_LDRH_REG, - A_UNK, A_LDRSB_REG, A_UNK, A_LDRSH_REG, + A_TST_REG_LSL_IMM, A_UNK, A_TST_REG_LSR_IMM, A_LDRH_REG, + A_TST_REG_ASR_IMM, A_LDRSB_REG, A_TST_REG_ROR_IMM, A_LDRSH_REG, // 0001 0010 0000 A_MSR_REG, A_BX, A_UNK, A_BLX_REG, @@ -120,8 +120,8 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) = // 0001 0011 0000 A_TEQ_REG_LSL_IMM, A_TEQ_REG_LSL_REG, A_TEQ_REG_LSR_IMM, A_TEQ_REG_LSR_REG, A_TEQ_REG_ASR_IMM, A_TEQ_REG_ASR_REG, A_TEQ_REG_ROR_IMM, A_TEQ_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_LDRH_REG, - A_UNK, A_LDRSB_REG, A_UNK, A_LDRSH_REG, + A_TEQ_REG_LSL_IMM, A_UNK, A_TEQ_REG_LSR_IMM, A_LDRH_REG, + A_TEQ_REG_ASR_IMM, A_LDRSB_REG, A_TEQ_REG_ROR_IMM, A_LDRSH_REG, // 0001 0100 0000 A_MRS, A_UNK, A_UNK, A_UNK, @@ -132,8 +132,8 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) = // 0001 0101 0000 A_CMP_REG_LSL_IMM, A_CMP_REG_LSL_REG, A_CMP_REG_LSR_IMM, A_CMP_REG_LSR_REG, A_CMP_REG_ASR_IMM, A_CMP_REG_ASR_REG, A_CMP_REG_ROR_IMM, A_CMP_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_LDRH_IMM, - A_UNK, A_LDRSB_IMM, A_UNK, A_LDRSH_IMM, + A_CMP_REG_LSL_IMM, A_UNK, A_CMP_REG_LSR_IMM, A_LDRH_IMM, + A_CMP_REG_ASR_IMM, A_LDRSB_IMM, A_CMP_REG_ROR_IMM, A_LDRSH_IMM, // 0001 0110 0000 A_MSR_REG, A_UNK, A_UNK, A_UNK, @@ -144,56 +144,56 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) = // 0001 0111 0000 A_CMN_REG_LSL_IMM, A_CMN_REG_LSL_REG, A_CMN_REG_LSR_IMM, A_CMN_REG_LSR_REG, A_CMN_REG_ASR_IMM, A_CMN_REG_ASR_REG, A_CMN_REG_ROR_IMM, A_CMN_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_LDRH_IMM, - A_UNK, A_LDRSB_IMM, A_UNK, A_LDRSH_IMM, + A_CMN_REG_LSL_IMM, A_UNK, A_CMN_REG_LSR_IMM, A_LDRH_IMM, + A_CMN_REG_ASR_IMM, A_LDRSB_IMM, A_CMN_REG_ROR_IMM, A_LDRSH_IMM, // 0001 1000 0000 A_ORR_REG_LSL_IMM, A_ORR_REG_LSL_REG, A_ORR_REG_LSR_IMM, A_ORR_REG_LSR_REG, A_ORR_REG_ASR_IMM, A_ORR_REG_ASR_REG, A_ORR_REG_ROR_IMM, A_ORR_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_STRH_REG, - A_UNK, A_LDRD_REG, A_UNK, A_STRD_REG, + A_ORR_REG_LSL_IMM, A_UNK, A_ORR_REG_LSR_IMM, A_STRH_REG, + A_ORR_REG_ASR_IMM, A_LDRD_REG, A_ORR_REG_ROR_IMM, A_STRD_REG, // 0001 1001 0000 A_ORR_REG_LSL_IMM_S, A_ORR_REG_LSL_REG_S, A_ORR_REG_LSR_IMM_S, A_ORR_REG_LSR_REG_S, A_ORR_REG_ASR_IMM_S, A_ORR_REG_ASR_REG_S, A_ORR_REG_ROR_IMM_S, A_ORR_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_LDRH_REG, - A_UNK, A_LDRSB_REG, A_UNK, A_LDRSH_REG, + A_ORR_REG_LSL_IMM_S, A_UNK, A_ORR_REG_LSR_IMM_S, A_LDRH_REG, + A_ORR_REG_ASR_IMM_S, A_LDRSB_REG, A_ORR_REG_ROR_IMM_S, A_LDRSH_REG, // 0001 1010 0000 A_MOV_REG_LSL_IMM, A_MOV_REG_LSL_REG, A_MOV_REG_LSR_IMM, A_MOV_REG_LSR_REG, A_MOV_REG_ASR_IMM, A_MOV_REG_ASR_REG, A_MOV_REG_ROR_IMM, A_MOV_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_STRH_REG, - A_UNK, A_LDRD_REG, A_UNK, A_STRD_REG, + A_MOV_REG_LSL_IMM, A_UNK, A_MOV_REG_LSR_IMM, A_STRH_REG, + A_MOV_REG_ASR_IMM, A_LDRD_REG, A_MOV_REG_ROR_IMM, A_STRD_REG, // 0001 1011 0000 A_MOV_REG_LSL_IMM_S, A_MOV_REG_LSL_REG_S, A_MOV_REG_LSR_IMM_S, A_MOV_REG_LSR_REG_S, A_MOV_REG_ASR_IMM_S, A_MOV_REG_ASR_REG_S, A_MOV_REG_ROR_IMM_S, A_MOV_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_LDRH_REG, - A_UNK, A_LDRSB_REG, A_UNK, A_LDRSH_REG, + A_MOV_REG_LSL_IMM_S, A_UNK, A_MOV_REG_LSR_IMM_S, A_LDRH_REG, + A_MOV_REG_ASR_IMM_S, A_LDRSB_REG, A_MOV_REG_ROR_IMM_S, A_LDRSH_REG, // 0001 1100 0000 A_BIC_REG_LSL_IMM, A_BIC_REG_LSL_REG, A_BIC_REG_LSR_IMM, A_BIC_REG_LSR_REG, A_BIC_REG_ASR_IMM, A_BIC_REG_ASR_REG, A_BIC_REG_ROR_IMM, A_BIC_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_STRH_IMM, - A_UNK, A_LDRD_IMM, A_UNK, A_STRD_IMM, + A_BIC_REG_LSL_IMM, A_UNK, A_BIC_REG_LSR_IMM, A_STRH_IMM, + A_BIC_REG_ASR_IMM, A_LDRD_IMM, A_BIC_REG_ROR_IMM, A_STRD_IMM, // 0001 1101 0000 A_BIC_REG_LSL_IMM_S, A_BIC_REG_LSL_REG_S, A_BIC_REG_LSR_IMM_S, A_BIC_REG_LSR_REG_S, A_BIC_REG_ASR_IMM_S, A_BIC_REG_ASR_REG_S, A_BIC_REG_ROR_IMM_S, A_BIC_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_LDRH_IMM, - A_UNK, A_LDRSB_IMM, A_UNK, A_LDRSH_IMM, + A_BIC_REG_LSL_IMM_S, A_UNK, A_BIC_REG_LSR_IMM_S, A_LDRH_IMM, + A_BIC_REG_ASR_IMM_S, A_LDRSB_IMM, A_BIC_REG_ROR_IMM_S, A_LDRSH_IMM, // 0001 1110 0000 A_MVN_REG_LSL_IMM, A_MVN_REG_LSL_REG, A_MVN_REG_LSR_IMM, A_MVN_REG_LSR_REG, A_MVN_REG_ASR_IMM, A_MVN_REG_ASR_REG, A_MVN_REG_ROR_IMM, A_MVN_REG_ROR_REG, - A_UNK, A_UNK, A_UNK, A_STRH_IMM, - A_UNK, A_LDRD_IMM, A_UNK, A_STRD_IMM, + A_MVN_REG_LSL_IMM, A_UNK, A_MVN_REG_LSR_IMM, A_STRH_IMM, + A_MVN_REG_ASR_IMM, A_LDRD_IMM, A_MVN_REG_ROR_IMM, A_STRD_IMM, // 0001 1111 0000 A_MVN_REG_LSL_IMM_S, A_MVN_REG_LSL_REG_S, A_MVN_REG_LSR_IMM_S, A_MVN_REG_LSR_REG_S, A_MVN_REG_ASR_IMM_S, A_MVN_REG_ASR_REG_S, A_MVN_REG_ROR_IMM_S, A_MVN_REG_ROR_REG_S, - A_UNK, A_UNK, A_UNK, A_LDRH_IMM, - A_UNK, A_LDRSB_IMM, A_UNK, A_LDRSH_IMM, + A_MVN_REG_LSL_IMM_S, A_UNK, A_MVN_REG_LSR_IMM_S, A_LDRH_IMM, + A_MVN_REG_ASR_IMM_S, A_LDRSB_IMM, A_MVN_REG_ROR_IMM_S, A_LDRSH_IMM, @@ -786,198 +786,198 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) = // 1000 0000 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1000 0001 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1000 0010 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1000 0011 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1000 0100 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1000 0101 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1000 0110 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1000 0111 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1000 1000 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1000 1001 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1000 1010 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1000 1011 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1000 1100 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1000 1101 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1000 1110 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1000 1111 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1001 0000 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1001 0001 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1001 0010 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1001 0011 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1001 0100 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1001 0101 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1001 0110 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1001 0111 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1001 1000 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1001 1001 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1001 1010 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1001 1011 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1001 1100 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1001 1101 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, // 1001 1110 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, + A_STM, A_STM, A_STM, A_STM, // 1001 1111 0000 - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, - A_UNK, A_UNK, A_UNK, A_UNK, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, + A_LDM, A_LDM, A_LDM, A_LDM, @@ -1607,16 +1607,16 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) = T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, T_ASR_IMM, // 0001 1000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_ADD_REG_, T_ADD_REG_, T_ADD_REG_, T_ADD_REG_, + T_ADD_REG_, T_ADD_REG_, T_ADD_REG_, T_ADD_REG_, + T_SUB_REG_, T_SUB_REG_, T_SUB_REG_, T_SUB_REG_, + T_SUB_REG_, T_SUB_REG_, T_SUB_REG_, T_SUB_REG_, // 0001 1100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_ADD_IMM_, T_ADD_IMM_, T_ADD_IMM_, T_ADD_IMM_, + T_ADD_IMM_, T_ADD_IMM_, T_ADD_IMM_, T_ADD_IMM_, + T_SUB_IMM_, T_SUB_IMM_, T_SUB_IMM_, T_SUB_IMM_, + T_SUB_IMM_, T_SUB_IMM_, T_SUB_IMM_, T_SUB_IMM_, // 0010 0000 00 T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, @@ -1675,9 +1675,9 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) = T_ORR_REG, T_MUL_REG, T_BIC_REG, T_MVN_REG, // 0100 0100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_UNK, T_ADD_HIREG, T_ADD_HIREG, T_ADD_HIREG, + T_UNK, T_CMP_HIREG, T_CMP_HIREG, T_CMP_HIREG, + T_UNK, T_MOV_HIREG, T_MOV_HIREG, T_MOV_HIREG, T_BX, T_BX, T_BLX_REG, T_BLX_REG, // 0100 1000 00 @@ -1717,52 +1717,52 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) = T_UNK, T_UNK, T_UNK, T_UNK, // 0110 0000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_STR_IMM, T_STR_IMM, T_STR_IMM, T_STR_IMM, + T_STR_IMM, T_STR_IMM, T_STR_IMM, T_STR_IMM, + T_STR_IMM, T_STR_IMM, T_STR_IMM, T_STR_IMM, + T_STR_IMM, T_STR_IMM, T_STR_IMM, T_STR_IMM, // 0110 0100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_STR_IMM, T_STR_IMM, T_STR_IMM, T_STR_IMM, + T_STR_IMM, T_STR_IMM, T_STR_IMM, T_STR_IMM, + T_STR_IMM, T_STR_IMM, T_STR_IMM, T_STR_IMM, + T_STR_IMM, T_STR_IMM, T_STR_IMM, T_STR_IMM, // 0110 1000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, + T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, + T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, + T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, // 0110 1100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, + T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, + T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, + T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, T_LDR_IMM, // 0111 0000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, + T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, + T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, + T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, // 0111 0100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, + T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, + T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, + T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, T_STRB_IMM, // 0111 1000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, + T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, + T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, + T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, // 0111 1100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, + T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, + T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, + T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, T_LDRB_IMM, @@ -1791,55 +1791,55 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) = T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, T_LDRH_IMM, // 1001 0000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, + T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, + T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, + T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, // 1001 0100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, + T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, + T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, + T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, T_STR_SPREL, // 1001 1000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, + T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, + T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, + T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, // 1001 1100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, + T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, + T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, + T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, T_LDR_SPREL, // 1010 0000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, + T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, + T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, + T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, // 1010 0100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, + T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, + T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, + T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, T_ADD_PCREL, // 1010 1000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, + T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, + T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, + T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, // 1010 1100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, + T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, + T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, + T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, T_ADD_SPREL, // 1011 0000 00 - T_UNK, T_UNK, T_UNK, T_UNK, + T_ADD_SP, T_ADD_SP, T_ADD_SP, T_ADD_SP, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, @@ -1913,16 +1913,16 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) = T_UNK, T_UNK, T_UNK, T_UNK, // 1110 0000 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_B, T_B, T_B, T_B, + T_B, T_B, T_B, T_B, + T_B, T_B, T_B, T_B, + T_B, T_B, T_B, T_B, // 1110 0100 00 - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, - T_UNK, T_UNK, T_UNK, T_UNK, + T_B, T_B, T_B, T_B, + T_B, T_B, T_B, T_B, + T_B, T_B, T_B, T_B, + T_B, T_B, T_B, T_B, // 1110 1000 00 T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, T_BL_LONG_2, diff --git a/NDS.cpp b/NDS.cpp index 7cf00b08..23a781a7 100644 --- a/NDS.cpp +++ b/NDS.cpp @@ -190,7 +190,7 @@ u32 ARM9Read32(u32 addr) return *(u32*)&MainRAM[addr & 0x3FFFFF]; } - printf("unknown arm9 read32 %08X\n", addr); + printf("unknown arm9 read32 %08X | %08X\n", addr, ARM9->R[15]); return 0; } @@ -341,8 +341,8 @@ u32 ARM7Read32(u32 addr) case 0x03800000: return *(u32*)&ARM7WRAM[addr & 0xFFFF]; } - - printf("unknown arm7 read32 %08X\n", addr); +if ((addr&0xFF000000) == 0xEA000000) Halt(); + printf("unknown arm7 read32 %08X | %08X\n", addr, ARM7->R[15]); return 0; } diff --git a/melonDS.depend b/melonDS.depend index 7309cf04..e36f7dd6 100644 --- a/melonDS.depend +++ b/melonDS.depend @@ -8,14 +8,14 @@ 1463409689 c:\documents\sources\melonds\types.h -1480776984 source:c:\documents\sources\melonds\nds.cpp +1480783776 source:c:\documents\sources\melonds\nds.cpp "NDS.h" "ARM.h" "CP15.h" -1480772238 source:c:\documents\sources\melonds\arm.cpp +1480779711 source:c:\documents\sources\melonds\arm.cpp "NDS.h" "ARM.h" @@ -25,7 +25,7 @@ "types.h" "NDS.h" -1480774506 c:\documents\sources\melonds\arm_instrtable.h +1480784235 c:\documents\sources\melonds\arm_instrtable.h 1480725698 c:\documents\sources\melonds\arminterpreter.h "types.h" @@ -41,20 +41,21 @@ "ARMInterpreter_LoadStore.h" "ARM_InstrTable.h" -1480771569 c:\documents\sources\melonds\arminterpreter_branch.h +1480783605 c:\documents\sources\melonds\arminterpreter_branch.h -1480772710 source:c:\documents\sources\melonds\arminterpreter_branch.cpp +1480783825 source:c:\documents\sources\melonds\arminterpreter_branch.cpp "ARM.h" -1480774402 c:\documents\sources\melonds\arminterpreter_alu.h +1480784137 c:\documents\sources\melonds\arminterpreter_alu.h -1480774326 source:c:\documents\sources\melonds\arminterpreter_alu.cpp +1480783339 source:c:\documents\sources\melonds\arminterpreter_alu.cpp "ARM.h" -1480771004 c:\documents\sources\melonds\arminterpreter_loadstore.h +1480780717 c:\documents\sources\melonds\arminterpreter_loadstore.h -1480770968 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp +1480783030 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp + "ARM.h" 1480776964 c:\documents\sources\melonds\cp15.h