compile UMULLs and some fixes
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1c07932b40
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1c98cefcee
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@ -301,10 +301,11 @@ void Compiler::A_Comp_MUL_MLA()
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Comp_MulOp(S, add, rd, rm, rs, rn);
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}
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void Compiler::A_Comp_SMULL_SMLAL()
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void Compiler::A_Comp_Mul_Long()
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{
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bool S = CurInstr.Instr & (1 << 20);
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bool add = CurInstr.Instr & (1 << 21);
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bool sign = CurInstr.Instr & (1 << 22);
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OpArg rd = MapReg(CurInstr.A_Reg(16));
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OpArg rm = MapReg(CurInstr.A_Reg(0));
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OpArg rs = MapReg(CurInstr.A_Reg(8));
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@ -318,18 +319,34 @@ void Compiler::A_Comp_SMULL_SMLAL()
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MOV(32, R(RSCRATCH3), rs);
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TEST(32, R(RSCRATCH3), R(RSCRATCH3));
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FixupBranch zeroBSR = J_CC(CC_Z);
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BSR(32, RSCRATCH2, R(RSCRATCH3));
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NOT(32, R(RSCRATCH3));
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BSR(32, RSCRATCH, R(RSCRATCH3));
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CMP(32, R(RSCRATCH2), R(RSCRATCH));
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CMOVcc(32, RSCRATCH, R(RSCRATCH2), CC_L);
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if (sign)
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{
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BSR(32, RSCRATCH2, R(RSCRATCH3));
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NOT(32, R(RSCRATCH3));
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BSR(32, RSCRATCH, R(RSCRATCH3));
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CMP(32, R(RSCRATCH2), R(RSCRATCH));
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CMOVcc(32, RSCRATCH, R(RSCRATCH2), CC_L);
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}
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else
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{
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BSR(32, RSCRATCH, R(RSCRATCH3));
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}
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SHR(32, R(RSCRATCH), Imm8(3));
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SetJumpTarget(zeroBSR); // fortunately that's even right
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Comp_AddCycles_CI(RSCRATCH, 2);
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}
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MOVSX(64, 32, RSCRATCH2, rm);
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MOVSX(64, 32, RSCRATCH3, rs);
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if (sign)
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{
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MOVSX(64, 32, RSCRATCH2, rm);
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MOVSX(64, 32, RSCRATCH3, rs);
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}
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else
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{
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MOV(32, R(RSCRATCH2), rm);
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MOV(32, R(RSCRATCH3), rs);
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}
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if (add)
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{
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MOV(32, R(RSCRATCH), rd);
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@ -300,7 +300,7 @@ const Compiler::CompileFunc A_Comp[ARMInstrInfo::ak_Count] =
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// CMN
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F(A_Comp_CmpOp), F(A_Comp_CmpOp), F(A_Comp_CmpOp), F(A_Comp_CmpOp), F(A_Comp_CmpOp), F(A_Comp_CmpOp), F(A_Comp_CmpOp), F(A_Comp_CmpOp), F(A_Comp_CmpOp),
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// Mul
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F(A_Comp_MUL_MLA), F(A_Comp_MUL_MLA), NULL, NULL, NULL, F(A_Comp_SMULL_SMLAL), NULL, NULL, NULL, NULL, NULL,
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F(A_Comp_MUL_MLA), F(A_Comp_MUL_MLA), F(A_Comp_Mul_Long), F(A_Comp_Mul_Long), F(A_Comp_Mul_Long), F(A_Comp_Mul_Long), NULL, NULL, NULL, NULL, NULL,
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// ARMv5 stuff
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F(A_Comp_CLZ), NULL, NULL, NULL, NULL,
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// STR
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@ -628,7 +628,7 @@ void Compiler::Comp_AddCycles_CI(Gen::X64Reg i, int add)
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}
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else
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{
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ConstantCycles += i + cycles;
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ConstantCycles += cycles;
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SUB(32, MDisp(RCPU, offsetof(ARM, Cycles)), R(i));
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}
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}
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@ -89,7 +89,7 @@ public:
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void A_Comp_CmpOp();
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void A_Comp_MUL_MLA();
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void A_Comp_SMULL_SMLAL();
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void A_Comp_Mul_Long();
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void A_Comp_CLZ();
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@ -423,7 +423,8 @@ void Compiler::Comp_MemAccess(int rd, int rn, const ComplexOperand& op2, int siz
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if (flags & memop_SubtractOffset)
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{
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MOV(32, R(finalAddr), rnMapped);
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if (R(finalAddr) != rnMapped)
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MOV(32, R(finalAddr), rnMapped);
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if (!offset.IsZero())
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SUB(32, R(finalAddr), offset);
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}
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