diff --git a/src/ARM.cpp b/src/ARM.cpp
index cf45a564..0d2976d2 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -1217,7 +1217,7 @@ bool ARMv4::DataWrite32(u32 addr, u32 val)
     return true;
 }
 
-bool ARMv4::DataWrite32S(u32 addr, u32 val)
+bool ARMv4::DataWrite32S(u32 addr, u32 val, bool dataabort)
 {
     addr &= ~3;
 
diff --git a/src/ARM.h b/src/ARM.h
index f2277253..1f68567c 100644
--- a/src/ARM.h
+++ b/src/ARM.h
@@ -135,7 +135,7 @@ public:
     virtual bool DataWrite8(u32 addr, u8 val) = 0;
     virtual bool DataWrite16(u32 addr, u16 val) = 0;
     virtual bool DataWrite32(u32 addr, u32 val) = 0;
-    virtual bool DataWrite32S(u32 addr, u32 val) = 0;
+    virtual bool DataWrite32S(u32 addr, u32 val, bool dataabort = false) = 0;
 
     virtual void AddCycles_C() = 0;
     virtual void AddCycles_CI(s32 numI) = 0;
@@ -256,7 +256,7 @@ public:
     bool DataWrite8(u32 addr, u8 val) override;
     bool DataWrite16(u32 addr, u16 val) override;
     bool DataWrite32(u32 addr, u32 val) override;
-    bool DataWrite32S(u32 addr, u32 val) override;
+    bool DataWrite32S(u32 addr, u32 val, bool dataabort = false) override;
 
     void AddCycles_C() override
     {
@@ -405,7 +405,7 @@ public:
     bool DataWrite8(u32 addr, u8 val) override;
     bool DataWrite16(u32 addr, u16 val) override;
     bool DataWrite32(u32 addr, u32 val) override;
-    bool DataWrite32S(u32 addr, u32 val) override;
+    bool DataWrite32S(u32 addr, u32 val, bool dataabort = false) override;
     void AddCycles_C() override;
     void AddCycles_CI(s32 num) override;
     void AddCycles_CDI() override;
diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index 67e09a7b..d28aed0f 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -273,7 +273,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     u32 r = (cpu->CurInstr>>12) & 0xF; \
     if (r&1) { r--; printf("!! MISALIGNED STRD %d\n", r+1); } \
     bool dataabort = !cpu->DataWrite32(offset, cpu->R[r  ]); /* yes, this data abort behavior is on purpose */ \
-    dataabort |= !cpu->DataWrite32S (offset+4, cpu->R[r+1]); /* no, i dont understand it either */ \
+    dataabort |= !cpu->DataWrite32S (offset+4, cpu->R[r+1], dataabort); /* no, i dont understand it either */ \
     cpu->AddCycles_CD(); \
     if (dataabort) return; \
     if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset;
@@ -284,7 +284,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     u32 r = (cpu->CurInstr>>12) & 0xF; \
     if (r&1) { r--; printf("!! MISALIGNED STRD_POST %d\n", r+1); } \
     bool dataabort = !cpu->DataWrite32(addr, cpu->R[r  ]); \
-    dataabort |= !cpu->DataWrite32S (addr+4, cpu->R[r+1]); \
+    dataabort |= !cpu->DataWrite32S (addr+4, cpu->R[r+1], dataabort); \
     cpu->AddCycles_CD(); \
     if (dataabort) return; \
     cpu->R[(cpu->CurInstr>>16) & 0xF] += offset;
diff --git a/src/CP15.cpp b/src/CP15.cpp
index 857c5c90..34c8addf 100644
--- a/src/CP15.cpp
+++ b/src/CP15.cpp
@@ -1014,11 +1014,11 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
     return true;
 }
 
-bool ARMv5::DataWrite32S(u32 addr, u32 val)
+bool ARMv5::DataWrite32S(u32 addr, u32 val, bool dataabort)
 {
     if (!(PU_Map[addr>>12] & 0x02))
     {
-        DataAbort();
+        if (!dataabort) DataAbort();
         return false;
     }