convert DSP
This commit is contained in:
Arisotura
parent
54ebf1b1b2
commit
11c22f077d
55
src/DSi.cpp
55
src/DSi.cpp
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@ -82,6 +82,7 @@ DSi_SDHost* SDIO;
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DSi_I2CHost* I2C;
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DSi_CamModule* CamModule;
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DSi_AES* AES;
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DSi_DSP* DSP;
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// FIXME: these currently have no effect (and aren't stored in a savestate)
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// ... not that they matter all that much
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@ -104,8 +105,6 @@ bool Init()
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NWRAM_C = new u8[NWRAMSize];
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#endif
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if (!DSi_DSP::Init()) return false;
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NDMAs[0] = new DSi_NDMA(0, 0);
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NDMAs[1] = new DSi_NDMA(0, 1);
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NDMAs[2] = new DSi_NDMA(0, 2);
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@ -121,6 +120,7 @@ bool Init()
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I2C = new DSi_I2CHost();
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CamModule = new DSi_CamModule();
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AES = new DSi_AES();
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DSP = new DSi_DSP();
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return true;
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}
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@ -137,8 +137,6 @@ void DeInit()
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NWRAM_C = nullptr;
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#endif
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DSi_DSP::DeInit();
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for (int i = 0; i < 8; i++)
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{
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delete NDMAs[i];
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@ -151,6 +149,7 @@ void DeInit()
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delete I2C; I2C = nullptr;
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delete CamModule; CamModule = nullptr;
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delete AES; AES = nullptr;
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delete DSP; DSP = nullptr;
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NANDImage = nullptr;
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// The NANDImage is cleaned up (and its underlying file closed)
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@ -170,7 +169,7 @@ void Reset()
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I2C->Reset();
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CamModule->Reset();
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DSi_DSP::Reset();
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DSP->Reset();
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SDMMC->CloseHandles();
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SDIO->CloseHandles();
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@ -197,7 +196,7 @@ void Reset()
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SCFG_MC = 0x0010 | (~((u32)(NDSCart::Cart != nullptr))&1);//0x0011;
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SCFG_RST = 0;
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DSi_DSP::SetRstLine(false);
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DSP->SetRstLine(false);
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GPIO_Data = 0xff; // these actually initialize to high after reset
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GPIO_Dir = 0x80; // enable sound out, all others input
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@ -239,7 +238,7 @@ void DoSavestate(Savestate* file)
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{
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Set_SCFG_Clock9(SCFG_Clock9);
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Set_SCFG_MC(SCFG_MC);
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DSi_DSP::SetRstLine(SCFG_RST & 0x0001);
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DSP->SetRstLine(SCFG_RST & 0x0001);
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MBK[0][8] = 0;
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MBK[1][8] = 0;
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@ -288,7 +287,7 @@ void DoSavestate(Savestate* file)
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AES->DoSavestate(file);
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CamModule->DoSavestate(file);
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DSi_DSP::DoSavestate(file);
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DSP->DoSavestate(file);
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I2C->DoSavestate(file);
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SDMMC->DoSavestate(file);
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SDIO->DoSavestate(file);
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@ -700,7 +699,7 @@ void SoftReset()
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// TODO: does the DSP get reset? NWRAM doesn't, so I'm assuming no
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// *HOWEVER*, the bootrom (which does get rerun) does remap NWRAM, and thus
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// the DSP most likely gets reset
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DSi_DSP::Reset();
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DSP->Reset();
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SDMMC->CloseHandles();
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SDIO->CloseHandles();
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@ -727,7 +726,7 @@ void SoftReset()
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SCFG_MC = 0x0010;//0x0011;
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// TODO: is this actually reset?
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SCFG_RST = 0;
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DSi_DSP::SetRstLine(false);
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DSP->SetRstLine(false);
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// LCD init flag
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@ -2310,7 +2309,7 @@ u8 ARM9IORead8(u32 addr)
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if ((addr & 0xFFFFFF00) == 0x04004300)
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{
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if (!(SCFG_EXT[0] & (1<<18))) return 0;
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return DSi_DSP::Read8(addr);
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return DSP->Read8(addr);
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}
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return NDS::ARM9IORead8(addr);
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@ -2345,7 +2344,7 @@ u16 ARM9IORead16(u32 addr)
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if ((addr & 0xFFFFFF00) == 0x04004300)
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{
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if (!(SCFG_EXT[0] & (1<<18))) return 0;
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return DSi_DSP::Read16(addr);
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return DSP->Read16(addr);
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}
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return NDS::ARM9IORead16(addr);
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@ -2410,7 +2409,7 @@ u32 ARM9IORead32(u32 addr)
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if ((addr & 0xFFFFFF00) == 0x04004300)
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{
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if (!(SCFG_EXT[0] & (1<<18))) return 0;
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return DSi_DSP::Read32(addr);
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return DSP->Read32(addr);
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}
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return NDS::ARM9IORead32(addr);
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@ -2434,7 +2433,7 @@ void ARM9IOWrite8(u32 addr, u8 val)
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if (!(SCFG_EXT[0] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
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SCFG_RST = (SCFG_RST & 0xFF00) | val;
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DSi_DSP::SetRstLine(val & 1);
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DSP->SetRstLine(val & 1);
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return;
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case 0x04004040:
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@ -2480,7 +2479,7 @@ void ARM9IOWrite8(u32 addr, u8 val)
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if ((addr & 0xFFFFFF00) == 0x04004300)
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{
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if (!(SCFG_EXT[0] & (1<<18))) return;
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return DSi_DSP::Write8(addr, val);
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return DSP->Write8(addr, val);
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}
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return NDS::ARM9IOWrite8(addr, val);
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@ -2500,7 +2499,7 @@ void ARM9IOWrite16(u32 addr, u16 val)
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if (!(SCFG_EXT[0] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
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SCFG_RST = val;
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DSi_DSP::SetRstLine(val & 1);
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DSP->SetRstLine(val & 1);
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return;
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case 0x04004040:
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@ -2540,7 +2539,7 @@ void ARM9IOWrite16(u32 addr, u16 val)
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if ((addr & 0xFFFFFF00) == 0x04004300)
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{
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if (!(SCFG_EXT[0] & (1<<18))) return;
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return DSi_DSP::Write16(addr, val);
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return DSP->Write16(addr, val);
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}
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return NDS::ARM9IOWrite16(addr, val);
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@ -2555,7 +2554,7 @@ void ARM9IOWrite32(u32 addr, u32 val)
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return;
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Set_SCFG_Clock9(val & 0xFFFF);
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SCFG_RST = val >> 16;
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DSi_DSP::SetRstLine((val >> 16) & 1);
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DSP->SetRstLine((val >> 16) & 1);
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break;
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case 0x04004008:
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@ -2690,7 +2689,7 @@ void ARM9IOWrite32(u32 addr, u32 val)
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if ((addr & 0xFFFFFF00) == 0x04004300)
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{
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if (!(SCFG_EXT[0] & (1<<18))) return;
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return DSi_DSP::Write32(addr, val);
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return DSP->Write32(addr, val);
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}
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return NDS::ARM9IOWrite32(addr, val);
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@ -2730,8 +2729,8 @@ u8 ARM7IORead8(u32 addr)
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case 0x04004D07: if (SCFG_BIOS & (1<<10)) return 0; return NANDImage->GetConsoleID() >> 56;
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case 0x04004D08: return 0;
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case 0x4004700: return DSi_DSP::SNDExCnt;
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case 0x4004701: return DSi_DSP::SNDExCnt >> 8;
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case 0x4004700: return DSP->ReadSNDExCnt() & 0xFF;
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case 0x4004701: return DSP->ReadSNDExCnt() >> 8;
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case 0x04004C00: return GPIO_Data;
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case 0x04004C01: return GPIO_Dir;
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@ -2773,7 +2772,7 @@ u16 ARM7IORead16(u32 addr)
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case 0x04004D06: if (SCFG_BIOS & (1<<10)) return 0; return NANDImage->GetConsoleID() >> 48;
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case 0x04004D08: return 0;
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case 0x4004700: return DSi_DSP::SNDExCnt;
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case 0x4004700: return DSP->ReadSNDExCnt();
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case 0x04004C00: return GPIO_Data | ((u16)GPIO_Dir << 8);
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case 0x04004C02: return GPIO_IEdgeSel | ((u16)GPIO_IE << 8);
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@ -2852,7 +2851,7 @@ u32 ARM7IORead32(u32 addr)
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case 0x4004700:
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Log(LogLevel::Debug, "32-Bit SNDExCnt read? %08X\n", NDS::ARM7->R[15]);
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return DSi_DSP::SNDExCnt;
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return DSP->ReadSNDExCnt();
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}
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if (addr >= 0x04004800 && addr < 0x04004A00)
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@ -2905,10 +2904,10 @@ void ARM7IOWrite8(u32 addr, u8 val)
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case 0x04004501: I2C->WriteCnt(val); return;
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case 0x4004700:
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DSi_DSP::WriteSNDExCnt((u16)val | (DSi_DSP::SNDExCnt & 0xFF00));
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DSP->WriteSNDExCnt((u16)val, 0xFF);
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return;
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case 0x4004701:
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DSi_DSP::WriteSNDExCnt(((u16)val << 8) | (DSi_DSP::SNDExCnt & 0x00FF));
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DSP->WriteSNDExCnt(((u16)val << 8), 0xFF00);
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return;
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case 0x04004C00:
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@ -3007,7 +3006,7 @@ void ARM7IOWrite16(u32 addr, u16 val)
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return;
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case 0x4004700:
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DSi_DSP::WriteSNDExCnt(val);
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DSP->WriteSNDExCnt(val, 0xFFFF);
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return;
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case 0x04004C00:
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@ -3156,7 +3155,7 @@ void ARM7IOWrite32(u32 addr, u32 val)
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case 0x4004700:
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Log(LogLevel::Debug, "32-Bit SNDExCnt write? %08X %08X\n", val, NDS::ARM7->R[15]);
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DSi_DSP::WriteSNDExCnt(val);
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DSP->WriteSNDExCnt(val, 0xFFFF);
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return;
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}
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@ -3204,7 +3203,7 @@ void ARM7IOWrite32(u32 addr, u32 val)
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if (addr >= 0x04004300 && addr <= 0x04004400)
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{
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DSi_DSP::Write32(addr, val);
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DSP->Write32(addr, val);
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return;
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}
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@ -25,6 +25,7 @@
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class DSi_I2CHost;
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class DSi_CamModule;
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class DSi_AES;
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class DSi_DSP;
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namespace DSi_NAND
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{
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@ -63,6 +64,7 @@ extern u32 NWRAMMask[2][3];
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extern DSi_I2CHost* I2C;
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extern DSi_CamModule* CamModule;
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extern DSi_AES* AES;
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extern DSi_DSP* DSP;
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bool Init();
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void DeInit();
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119
src/DSi_DSP.cpp
119
src/DSi_DSP.cpp
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@ -27,34 +27,12 @@
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using Platform::Log;
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using Platform::LogLevel;
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namespace DSi_DSP
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{
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// not sure whether to not rather put it somewhere else
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u16 SNDExCnt;
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Teakra::Teakra* TeakraCore;
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bool SCFG_RST;
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u16 DSP_PADR;
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u16 DSP_PCFG;
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u16 DSP_PSTS;
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u16 DSP_PSEM;
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u16 DSP_PMASK;
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u16 DSP_PCLEAR;
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u16 DSP_CMD[3];
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u16 DSP_REP[3];
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u64 DSPTimestamp;
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FIFO<u16, 16> PDATAReadFifo/*, *PDATAWriteFifo*/;
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int PDataDMALen = 0;
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constexpr u32 DataMemoryOffset = 0x20000; // from Teakra memory_interface.h
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const u32 DSi_DSP::DataMemoryOffset = 0x20000; // from Teakra memory_interface.h
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// NOTE: ^ IS IN DSP WORDS, NOT IN BYTES!
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u16 GetPSTS()
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u16 DSi_DSP::GetPSTS()
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{
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u16 r = DSP_PSTS & (1<<9); // this is the only sticky bit
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//r &= ~((1<<2)|(1<<7)); // we support instant resets and wrfifo xfers
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@ -73,26 +51,26 @@ u16 GetPSTS()
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return r;
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}
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void IrqRep0()
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void DSi_DSP::IrqRep0()
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{
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if (DSP_PCFG & (1<< 9)) NDS::SetIRQ(0, NDS::IRQ_DSi_DSP);
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}
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void IrqRep1()
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void DSi_DSP::IrqRep1()
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{
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if (DSP_PCFG & (1<<10)) NDS::SetIRQ(0, NDS::IRQ_DSi_DSP);
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}
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void IrqRep2()
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void DSi_DSP::IrqRep2()
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{
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if (DSP_PCFG & (1<<11)) NDS::SetIRQ(0, NDS::IRQ_DSi_DSP);
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}
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void IrqSem()
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void DSi_DSP::IrqSem()
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{
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DSP_PSTS |= 1<<9;
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// apparently these are always fired?
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NDS::SetIRQ(0, NDS::IRQ_DSi_DSP);
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}
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u16 DSPRead16(u32 addr)
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u16 DSi_DSP::DSPRead16(u32 addr)
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{
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if (!(addr & 0x40000))
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{
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@ -106,7 +84,7 @@ u16 DSPRead16(u32 addr)
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}
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}
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void DSPWrite16(u32 addr, u16 val)
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void DSi_DSP::DSPWrite16(u32 addr, u16 val)
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{
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// TODO: does the rule for overlapping NWRAM slots also apply to the DSP side?
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@ -122,29 +100,32 @@ void DSPWrite16(u32 addr, u16 val)
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}
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}
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void AudioCb(std::array<s16, 2> frame)
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void DSi_DSP::AudioCb(std::array<s16, 2> frame)
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{
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// TODO
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}
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bool Init()
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DSi_DSP::DSi_DSP()
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{
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NDS::RegisterEventFunc(NDS::Event_DSi_DSP, 0, DSPCatchUpU32);
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NDS::RegisterEventFunc(NDS::Event_DSi_DSP, 0, MemberEventFunc(DSi_DSP, DSPCatchUpU32));
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TeakraCore = new Teakra::Teakra();
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SCFG_RST = false;
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if (!TeakraCore) return false;
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// ????
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//if (!TeakraCore) return false;
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TeakraCore->SetRecvDataHandler(0, IrqRep0);
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TeakraCore->SetRecvDataHandler(1, IrqRep1);
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TeakraCore->SetRecvDataHandler(2, IrqRep2);
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using namespace std::placeholders;
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TeakraCore->SetSemaphoreHandler(IrqSem);
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TeakraCore->SetRecvDataHandler(0, std::bind(&DSi_DSP::IrqRep0, this));
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TeakraCore->SetRecvDataHandler(1, std::bind(&DSi_DSP::IrqRep1, this));
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TeakraCore->SetRecvDataHandler(2, std::bind(&DSi_DSP::IrqRep2, this));
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TeakraCore->SetSemaphoreHandler(std::bind(&DSi_DSP::IrqSem, this));
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Teakra::SharedMemoryCallback smcb;
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smcb.read16 = DSPRead16;
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smcb.write16 = DSPWrite16;
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smcb.read16 = std::bind(&DSi_DSP::DSPRead16, this, _1);
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smcb.write16 = std::bind(&DSi_DSP::DSPWrite16, this, _1, _2);
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TeakraCore->SetSharedMemoryCallback(smcb);
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// these happen instantaneously and without too much regard for bus aribtration
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@ -158,14 +139,13 @@ bool Init()
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cb.write32 = DSi::ARM9Write32;
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TeakraCore->SetAHBMCallback(cb);
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TeakraCore->SetAudioCallback(AudioCb);
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TeakraCore->SetAudioCallback(std::bind(&DSi_DSP::AudioCb, this, _1));
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//PDATAReadFifo = new FIFO<u16>(16);
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//PDATAWriteFifo = new FIFO<u16>(16);
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return true;
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}
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void DeInit()
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DSi_DSP::~DSi_DSP()
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{
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//if (PDATAWriteFifo) delete PDATAWriteFifo;
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if (TeakraCore) delete TeakraCore;
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@ -177,7 +157,7 @@ void DeInit()
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NDS::UnregisterEventFunc(NDS::Event_DSi_DSP, 0);
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}
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void Reset()
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void DSi_DSP::Reset()
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{
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DSPTimestamp = 0;
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@ -200,28 +180,28 @@ void Reset()
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SNDExCnt = 0;
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}
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bool IsRstReleased()
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bool DSi_DSP::IsRstReleased()
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{
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return SCFG_RST;
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}
|
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void SetRstLine(bool release)
|
||||
void DSi_DSP::SetRstLine(bool release)
|
||||
{
|
||||
SCFG_RST = release;
|
||||
Reset();
|
||||
DSPTimestamp = NDS::ARM9Timestamp; // only start now!
|
||||
}
|
||||
|
||||
inline bool IsDSPCoreEnabled()
|
||||
inline bool DSi_DSP::IsDSPCoreEnabled()
|
||||
{
|
||||
return (DSi::SCFG_Clock9 & (1<<1)) && SCFG_RST && (!(DSP_PCFG & (1<<0)));
|
||||
}
|
||||
|
||||
inline bool IsDSPIOEnabled()
|
||||
inline bool DSi_DSP::IsDSPIOEnabled()
|
||||
{
|
||||
return (DSi::SCFG_Clock9 & (1<<1)) && SCFG_RST;
|
||||
}
|
||||
|
||||
bool DSPCatchUp()
|
||||
bool DSi_DSP::DSPCatchUp()
|
||||
{
|
||||
//asm volatile("int3");
|
||||
if (!IsDSPCoreEnabled())
|
||||
|
|
@ -249,9 +229,9 @@ bool DSPCatchUp()
|
|||
|
||||
return true;
|
||||
}
|
||||
void DSPCatchUpU32(u32 _) { DSPCatchUp(); }
|
||||
void DSi_DSP::DSPCatchUpU32(u32 _) { DSPCatchUp(); }
|
||||
|
||||
void PDataDMAWrite(u16 wrval)
|
||||
void DSi_DSP::PDataDMAWrite(u16 wrval)
|
||||
{
|
||||
u32 addr = DSP_PADR;
|
||||
|
||||
|
|
@ -293,7 +273,7 @@ void PDataDMAWrite(u16 wrval)
|
|||
NDS::SetIRQ(0, NDS::IRQ_DSi_DSP); // wrfifo empty
|
||||
}
|
||||
// TODO: FIFO interrupts! (rd full, nonempty)
|
||||
u16 PDataDMARead()
|
||||
u16 DSi_DSP::PDataDMARead()
|
||||
{
|
||||
u16 r = 0;
|
||||
u32 addr = DSP_PADR;
|
||||
|
|
@ -331,7 +311,7 @@ u16 PDataDMARead()
|
|||
|
||||
return r;
|
||||
}
|
||||
void PDataDMAFetch()
|
||||
void DSi_DSP::PDataDMAFetch()
|
||||
{
|
||||
if (!PDataDMALen) return;
|
||||
|
||||
|
|
@ -339,7 +319,7 @@ void PDataDMAFetch()
|
|||
|
||||
if (PDataDMALen > 0) --PDataDMALen;
|
||||
}
|
||||
void PDataDMAStart()
|
||||
void DSi_DSP::PDataDMAStart()
|
||||
{
|
||||
switch ((DSP_PSTS & (3<<2)) >> 2)
|
||||
{
|
||||
|
|
@ -358,13 +338,13 @@ void PDataDMAStart()
|
|||
NDS::SetIRQ(0, NDS::IRQ_DSi_DSP);
|
||||
|
||||
}
|
||||
void PDataDMACancel()
|
||||
void DSi_DSP::PDataDMACancel()
|
||||
{
|
||||
PDataDMALen = 0;
|
||||
PDATAReadFifo.Clear();
|
||||
|
||||
}
|
||||
u16 PDataDMAReadMMIO()
|
||||
u16 DSi_DSP::PDataDMAReadMMIO()
|
||||
{
|
||||
u16 ret;
|
||||
|
||||
|
|
@ -395,7 +375,7 @@ u16 PDataDMAReadMMIO()
|
|||
return ret;
|
||||
}
|
||||
|
||||
u8 Read8(u32 addr)
|
||||
u8 DSi_DSP::Read8(u32 addr)
|
||||
{
|
||||
//if (!IsDSPIOEnabled()) return 0;
|
||||
DSPCatchUp();
|
||||
|
|
@ -422,7 +402,7 @@ u8 Read8(u32 addr)
|
|||
|
||||
return 0;
|
||||
}
|
||||
u16 Read16(u32 addr)
|
||||
u16 DSi_DSP::Read16(u32 addr)
|
||||
{
|
||||
//printf("DSP READ16 %d %08X %08X\n", IsDSPCoreEnabled(), addr, NDS::GetPC(0));
|
||||
//if (!IsDSPIOEnabled()) return 0;
|
||||
|
|
@ -465,14 +445,14 @@ u16 Read16(u32 addr)
|
|||
|
||||
return 0;
|
||||
}
|
||||
u32 Read32(u32 addr)
|
||||
u32 DSi_DSP::Read32(u32 addr)
|
||||
{
|
||||
addr &= 0x3C;
|
||||
return Read16(addr); // *shrug* (doesn't do anything unintended due to the
|
||||
// 4byte spacing between regs while they're all 16bit)
|
||||
}
|
||||
|
||||
void Write8(u32 addr, u8 val)
|
||||
void DSi_DSP::Write8(u32 addr, u8 val)
|
||||
{
|
||||
//if (!IsDSPIOEnabled()) return;
|
||||
DSPCatchUp();
|
||||
|
|
@ -493,7 +473,7 @@ void Write8(u32 addr, u8 val)
|
|||
// no REPx writes
|
||||
}
|
||||
}
|
||||
void Write16(u32 addr, u16 val)
|
||||
void DSi_DSP::Write16(u32 addr, u16 val)
|
||||
{
|
||||
Log(LogLevel::Debug,"DSP WRITE16 %d %08X %08X %08X\n", IsDSPCoreEnabled(), addr, val, NDS::GetPC(0));
|
||||
//if (!IsDSPIOEnabled()) return;
|
||||
|
|
@ -548,14 +528,16 @@ void Write16(u32 addr, u16 val)
|
|||
}
|
||||
}
|
||||
|
||||
void Write32(u32 addr, u32 val)
|
||||
void DSi_DSP::Write32(u32 addr, u32 val)
|
||||
{
|
||||
addr &= 0x3C;
|
||||
Write16(addr, val & 0xFFFF);
|
||||
}
|
||||
|
||||
void WriteSNDExCnt(u16 val)
|
||||
void DSi_DSP::WriteSNDExCnt(u16 val, u16 mask)
|
||||
{
|
||||
val = (val & mask) | (SNDExCnt & ~mask);
|
||||
|
||||
// it can be written even in NDS mode
|
||||
|
||||
// mic frequency can only be changed if it was disabled
|
||||
|
|
@ -569,7 +551,7 @@ void WriteSNDExCnt(u16 val)
|
|||
SNDExCnt = val & 0xE00F;
|
||||
}
|
||||
|
||||
void Run(u32 cycles)
|
||||
void DSi_DSP::Run(u32 cycles)
|
||||
{
|
||||
if (!IsDSPCoreEnabled())
|
||||
{
|
||||
|
|
@ -586,7 +568,7 @@ void Run(u32 cycles)
|
|||
16384/*from citra (TeakraSlice)*/, 0, 0);
|
||||
}
|
||||
|
||||
void DoSavestate(Savestate* file)
|
||||
void DSi_DSP::DoSavestate(Savestate* file)
|
||||
{
|
||||
file->Section("DSPi");
|
||||
|
||||
|
|
@ -611,6 +593,3 @@ void DoSavestate(Savestate* file)
|
|||
|
||||
// TODO: save the Teakra state!!!
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,50 +25,84 @@
|
|||
// TODO: for actual sound output
|
||||
// * audio callbacks
|
||||
|
||||
namespace DSi_DSP
|
||||
namespace Teakra { class Teakra; }
|
||||
|
||||
class DSi_DSP
|
||||
{
|
||||
public:
|
||||
DSi_DSP();
|
||||
~DSi_DSP();
|
||||
void Reset();
|
||||
void DoSavestate(Savestate* file);
|
||||
|
||||
extern u16 SNDExCnt;
|
||||
void DSPCatchUpU32(u32 _);
|
||||
|
||||
extern u16 DSP_PDATA;
|
||||
extern u16 DSP_PADR;
|
||||
extern u16 DSP_PCFG;
|
||||
extern u16 DSP_PSTS;
|
||||
extern u16 DSP_PSEM;
|
||||
extern u16 DSP_PMASK;
|
||||
extern u16 DSP_PCLEAR;
|
||||
extern u16 DSP_SEM;
|
||||
extern u16 DSP_CMD[3];
|
||||
extern u16 DSP_REP[3];
|
||||
// SCFG_RST bit0
|
||||
bool IsRstReleased();
|
||||
void SetRstLine(bool release);
|
||||
|
||||
bool Init();
|
||||
void DeInit();
|
||||
void Reset();
|
||||
// DSP_* regs (0x040043xx) (NOTE: checks SCFG_EXT)
|
||||
u8 Read8(u32 addr);
|
||||
void Write8(u32 addr, u8 val);
|
||||
|
||||
void DoSavestate(Savestate* file);
|
||||
u16 Read16(u32 addr);
|
||||
void Write16(u32 addr, u16 val);
|
||||
|
||||
void DSPCatchUpU32(u32 _);
|
||||
u32 Read32(u32 addr);
|
||||
void Write32(u32 addr, u32 val);
|
||||
|
||||
// SCFG_RST bit0
|
||||
bool IsRstReleased();
|
||||
void SetRstLine(bool release);
|
||||
u16 ReadSNDExCnt() { return SNDExCnt; }
|
||||
void WriteSNDExCnt(u16 val, u16 mask);
|
||||
|
||||
// DSP_* regs (0x040043xx) (NOTE: checks SCFG_EXT)
|
||||
u8 Read8(u32 addr);
|
||||
void Write8(u32 addr, u8 val);
|
||||
// NOTE: checks SCFG_CLK9
|
||||
void Run(u32 cycles);
|
||||
|
||||
u16 Read16(u32 addr);
|
||||
void Write16(u32 addr, u16 val);
|
||||
void IrqRep0();
|
||||
void IrqRep1();
|
||||
void IrqRep2();
|
||||
void IrqSem();
|
||||
u16 DSPRead16(u32 addr);
|
||||
void DSPWrite16(u32 addr, u16 val);
|
||||
void AudioCb(std::array<s16, 2> frame);
|
||||
|
||||
u32 Read32(u32 addr);
|
||||
void Write32(u32 addr, u32 val);
|
||||
private:
|
||||
// not sure whether to not rather put it somewhere else
|
||||
u16 SNDExCnt;
|
||||
|
||||
void WriteSNDExCnt(u16 val);
|
||||
Teakra::Teakra* TeakraCore;
|
||||
|
||||
// NOTE: checks SCFG_CLK9
|
||||
void Run(u32 cycles);
|
||||
bool SCFG_RST;
|
||||
|
||||
}
|
||||
u16 DSP_PADR;
|
||||
u16 DSP_PCFG;
|
||||
u16 DSP_PSTS;
|
||||
u16 DSP_PSEM;
|
||||
u16 DSP_PMASK;
|
||||
u16 DSP_PCLEAR;
|
||||
u16 DSP_CMD[3];
|
||||
u16 DSP_REP[3];
|
||||
|
||||
u64 DSPTimestamp;
|
||||
|
||||
FIFO<u16, 16> PDATAReadFifo/*, *PDATAWriteFifo*/;
|
||||
int PDataDMALen;
|
||||
|
||||
static const u32 DataMemoryOffset;
|
||||
|
||||
u16 GetPSTS();
|
||||
|
||||
inline bool IsDSPCoreEnabled();
|
||||
inline bool IsDSPIOEnabled();
|
||||
|
||||
bool DSPCatchUp();
|
||||
|
||||
void PDataDMAWrite(u16 wrval);
|
||||
u16 PDataDMARead();
|
||||
void PDataDMAFetch();
|
||||
void PDataDMAStart();
|
||||
void PDataDMACancel();
|
||||
u16 PDataDMAReadMMIO();
|
||||
};
|
||||
|
||||
#endif // DSI_DSP_H
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue