diff --git a/src/ARM.cpp b/src/ARM.cpp
index 7b8fbf46..75d88aea 100644
--- a/src/ARM.cpp
+++ b/src/ARM.cpp
@@ -1184,14 +1184,14 @@ void ARMv5::HandleInterlocksExecute(u16 ilmask)
 {
     if ((bitfield && (ilmask & (1<<ILCurrReg))) || (!bitfield && (ilmask == ILCurrReg)))
     {
-        if (NDS.ARM9Timestamp > ILCurrTime) NDS.ARM9Timestamp = ILCurrTime;
+        if (NDS.ARM9Timestamp < ILCurrTime) NDS.ARM9Timestamp = ILCurrTime;
         ILCurrReg = 16;
         ILPrevReg = 16;
         return;
     }
     else if ((bitfield && (ilmask & (1<<ILPrevReg))) || (!bitfield && (ilmask == ILCurrReg)))
     {
-        if (NDS.ARM9Timestamp > ILPrevTime) NDS.ARM9Timestamp = ILPrevTime;
+        if (NDS.ARM9Timestamp < ILPrevTime) NDS.ARM9Timestamp = ILPrevTime;
     }
 
     ILPrevReg = ILCurrReg;
@@ -1203,7 +1203,7 @@ template void ARMv5::HandleInterlocksExecute<false>(u16 ilmask);
 
 void ARMv5::HandleInterlocksMemory(u8 reg)
 {
-    if ((reg != ILPrevReg) || (NDS.ARM9Timestamp <= ILPrevTime)) return;
+    if ((reg != ILPrevReg) || (NDS.ARM9Timestamp >= ILPrevTime)) return;
 
     NDS.ARM9Timestamp = ILPrevTime;
     ILPrevTime = 16;
diff --git a/src/ARMInterpreter_ALU.cpp b/src/ARMInterpreter_ALU.cpp
index 0d2fb5af..ce2a0cd7 100644
--- a/src/ARMInterpreter_ALU.cpp
+++ b/src/ARMInterpreter_ALU.cpp
@@ -897,7 +897,7 @@ void A_MUL(ARM* cpu)
             cpu->DataRegion = Mem9_Null;
             ((ARMv5*)cpu)->AddCycles_MW(2); // 2 M
             ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF;
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
         }
     }
     else
@@ -943,7 +943,7 @@ void A_MLA(ARM* cpu)
             cpu->DataRegion = Mem9_Null;
             ((ARMv5*)cpu)->AddCycles_MW(2); // 2 M
             ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF;
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
         }
     }
     else
@@ -989,7 +989,7 @@ void A_UMULL(ARM* cpu)
             cpu->DataRegion = Mem9_Null;
             ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
             ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
         }
     }
     else
@@ -1040,7 +1040,7 @@ void A_UMLAL(ARM* cpu)
             cpu->DataRegion = Mem9_Null;
             ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
             ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
         }
     }
     else
@@ -1086,7 +1086,7 @@ void A_SMULL(ARM* cpu)
             cpu->DataRegion = Mem9_Null;
             ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
             ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
         }
     }
     else
@@ -1136,7 +1136,7 @@ void A_SMLAL(ARM* cpu)
             cpu->DataRegion = Mem9_Null;
             ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
             ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
         }
     }
     else
@@ -1181,7 +1181,7 @@ void A_SMLAxy(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 void A_SMLAWy(ARM* cpu)
@@ -1212,7 +1212,7 @@ void A_SMLAWy(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 void A_SMULxy(ARM* cpu)
@@ -1240,7 +1240,7 @@ void A_SMULxy(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 void A_SMULWy(ARM* cpu)
@@ -1266,7 +1266,7 @@ void A_SMULWy(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 void A_SMLALxy(ARM* cpu)
@@ -1302,7 +1302,7 @@ void A_SMLALxy(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(2); // 2 M
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 16) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 
@@ -1358,7 +1358,7 @@ void A_QADD(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 12) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 void A_QSUB(ARM* cpu)
@@ -1384,7 +1384,7 @@ void A_QSUB(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 12) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 void A_QDADD(ARM* cpu)
@@ -1418,7 +1418,7 @@ void A_QDADD(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 12) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 void A_QDSUB(ARM* cpu)
@@ -1452,7 +1452,7 @@ void A_QDSUB(ARM* cpu)
     cpu->DataRegion = Mem9_Null;
     ((ARMv5*)cpu)->AddCycles_MW(1); // dummy memory stage for interlock handling
     ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 12) & 0xF; // only one rd interlocks
-    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
 }
 
 
diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index 3022b94d..93ea54dc 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -132,7 +132,7 @@ void LoadSingle(ARM* cpu, u8 rd, u8 rn, s32 offset, u16 ilmask)
         {
             ((ARMv5*)cpu)->ILCurrReg = rd;
             bool extra = ((size < 32) || (signror && (addr&0x3)));
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles + extra;
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + extra;
         }
     }
 }
@@ -322,7 +322,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
         cpu->R[r+1] = val; \
         if (cpu->Num == 0) { \
             ((ARMv5*)cpu)->ILCurrReg = r+1; \
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles; } } \
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual; } } \
     if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset;
 
 #define A_LDRD_POST \
@@ -342,7 +342,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
         cpu->R[r+1] = val; \
         if (cpu->Num == 0) { \
             ((ARMv5*)cpu)->ILCurrReg = r+1; \
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles; } } \
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual; } } \
     cpu->R[(cpu->CurInstr>>16) & 0xF] += offset;
 
 #define A_STRD \
@@ -464,7 +464,7 @@ inline void SWP(ARM* cpu)
                 {
                     ((ARMv5*)cpu)->ILCurrReg = rd;
                     bool extra = (byte || (base&0x3));
-                    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles + extra;
+                    ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + extra;
                 }
             }
             else if (cpu->Num==1) cpu->JumpTo(val & ~1); // for some reason these jumps don't seem to work on the arm 9?
@@ -651,7 +651,7 @@ void A_LDM(ARM* cpu)
     {
         u8 lastreg = 31 - __builtin_clz(cpu->CurInstr & 0x7FFF);
         ((ARMv5*)cpu)->ILCurrReg = lastreg;
-        ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+        ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
     }
 }
 
@@ -766,7 +766,7 @@ void T_LDR_PCREL(ARM* cpu)
     else if (cpu->Num == 0)
     {
         ((ARMv5*)cpu)->ILCurrReg = (cpu->CurInstr >> 8) & 0x7;
-        ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+        ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
     }
 }
 
@@ -967,7 +967,7 @@ void T_POP(ARM* cpu)
         {
             u8 lastreg = 31 - __builtin_clz(cpu->CurInstr & 0xFF);
             ((ARMv5*)cpu)->ILCurrReg = lastreg;
-            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+            ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
         }
     }
 
@@ -1064,7 +1064,7 @@ void T_LDMIA(ARM* cpu)
     {
         u8 lastreg = 31 - __builtin_clz(cpu->CurInstr & 0xFF);
         ((ARMv5*)cpu)->ILCurrReg = lastreg;
-        ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual + ((ARMv5*)cpu)->DataCycles;
+        ((ARMv5*)cpu)->ILCurrTime = ((ARMv5*)cpu)->TimestampActual;
     }
 
     if (!(cpu->CurInstr & (1<<((cpu->CurInstr >> 8) & 0x7))))