load register only if needed
- do thumb bl long merge in the first step - preparations for better branch jitting
This commit is contained in:
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85680d6fe5
commit
0e26aa4ede
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@ -159,6 +159,7 @@ CompiledBlock CompileBlock(ARM* cpu)
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u32 r15 = cpu->R[15];
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cpu->FillPipeline();
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u32 nextInstr[2] = {cpu->NextInstr[0], cpu->NextInstr[1]};
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u32 nextInstrAddr[2] = {blockAddr, r15};
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do
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{
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r15 += thumb ? 2 : 4;
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@ -166,6 +167,10 @@ CompiledBlock CompileBlock(ARM* cpu)
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instrs[i].SetFlags = 0;
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instrs[i].Instr = nextInstr[0];
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instrs[i].NextInstr[0] = nextInstr[0] = nextInstr[1];
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instrs[i].Addr = nextInstrAddr[0];
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nextInstrAddr[0] = nextInstrAddr[1];
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nextInstrAddr[1] = r15;
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if (cpu->Num == 0)
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{
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@ -193,8 +198,19 @@ CompiledBlock CompileBlock(ARM* cpu)
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instrs[i].NextInstr[1] = nextInstr[1];
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instrs[i].Info = ARMInstrInfo::Decode(thumb, cpu->Num, instrs[i].Instr);
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if (thumb && instrs[i].Info.Kind == ARMInstrInfo::tk_BL_LONG_2 && i > 0
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&& instrs[i - 1].Info.Kind == ARMInstrInfo::tk_BL_LONG_1)
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{
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instrs[i - 1].Info.Kind = ARMInstrInfo::tk_BL_LONG;
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instrs[i - 1].Instr = (instrs[i - 1].Instr & 0xFFFF) | (instrs[i].Instr << 16);
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instrs[i - 1].Info.DstRegs = 0xC000;
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instrs[i - 1].Info.SrcRegs = 0;
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instrs[i - 1].Info.EndBlock = true;
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i--;
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}
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i++;
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bool canCompile = compiler->CanCompile(thumb, instrs[i - 1].Info.Kind);
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if (instrs[i - 1].Info.ReadFlags != 0 || !canCompile)
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floodFillSetFlags(instrs, i - 2, canCompile ? instrs[i - 1].Info.ReadFlags : 0xF);
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@ -31,6 +31,7 @@ struct FetchedInstr
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u8 SetFlags;
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u32 Instr;
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u32 NextInstr[2];
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u32 Addr;
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u8 CodeCycles;
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@ -38,7 +38,7 @@ public:
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Mapping[reg] = (Reg)-1;
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}
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void LoadRegister(int reg)
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void LoadRegister(int reg, bool loadValue)
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{
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assert(Mapping[reg] == -1);
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for (int i = 0; i < NativeRegsAvailable; i++)
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@ -50,7 +50,8 @@ public:
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NativeRegsUsed |= 1 << (int)nativeReg;
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LoadedRegs |= 1 << reg;
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Compiler->LoadReg(reg, nativeReg);
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if (loadValue)
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Compiler->LoadReg(reg, nativeReg);
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return;
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}
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@ -66,7 +67,7 @@ public:
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UnloadRegister(reg);
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}
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void Prepare(int i)
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void Prepare(bool thumb, int i)
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{
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u16 futureNeeded = 0;
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int ranking[16];
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@ -111,8 +112,11 @@ public:
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loadedSet.m_val = LoadedRegs;
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}
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BitSet16 needValueLoaded(needToBeLoaded);
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if (thumb || Instr.Cond() >= 0xE)
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needValueLoaded = BitSet16(Instr.Info.SrcRegs);
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for (int reg : needToBeLoaded)
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LoadRegister(reg);
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LoadRegister(reg, needValueLoaded[reg]);
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}
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DirtyRegs |= Instr.Info.DstRegs & ~(1 << 15);
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}
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@ -271,15 +271,17 @@ void Compiler::T_Comp_BL_LONG_2()
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Comp_JumpTo(RSCRATCH);
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}
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void Compiler::T_Comp_BL_Merged(FetchedInstr part1)
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void Compiler::T_Comp_BL_Merged()
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{
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assert(part1.Info.Kind == ARMInstrInfo::tk_BL_LONG_1);
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Comp_AddCycles_C();
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u32 target = (R15 - 2) + ((s32)((part1.Instr & 0x7FF) << 21) >> 9);
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target += (CurInstr.Instr & 0x7FF) << 1;
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R15 += 2;
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if (Num == 1 || CurInstr.Instr & (1 << 12))
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u32 upperPart = CurInstr.Instr >> 16;
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u32 target = (R15 - 2) + ((s32)((CurInstr.Instr & 0x7FF) << 21) >> 9);
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target += (upperPart & 0x7FF) << 1;
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if (Num == 1 || upperPart & (1 << 12))
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target |= 1;
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MOV(32, MapReg(14), Imm32((R15 - 2) | 1));
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@ -338,7 +338,8 @@ const Compiler::CompileFunc T_Comp[ARMInstrInfo::tk_Count] = {
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// Branch
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F(T_Comp_BCOND), F(T_Comp_BranchXchangeReg), F(T_Comp_BranchXchangeReg), F(T_Comp_B), F(T_Comp_BL_LONG_1), F(T_Comp_BL_LONG_2),
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// Unk, SVC
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NULL, NULL
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NULL, NULL,
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F(T_Comp_BL_Merged)
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};
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#undef F
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@ -361,21 +362,18 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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ConstantCycles = 0;
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Thumb = cpu->CPSR & 0x20;
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Num = cpu->Num;
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R15 = cpu->R[15];
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CodeRegion = cpu->CodeRegion;
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CurCPU = cpu;
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CompiledBlock res = (CompiledBlock)GetWritableCodePtr();
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if (!(Num == 0
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? IsMapped<0>(R15 - (Thumb ? 2 : 4))
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: IsMapped<1>(R15 - (Thumb ? 2 : 4))))
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? IsMapped<0>(instrs[0].Addr - (Thumb ? 2 : 4))
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: IsMapped<1>(instrs[0].Addr - (Thumb ? 2 : 4))))
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{
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printf("Trying to compile a block in unmapped memory\n");
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}
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bool mergedThumbBL = false;
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ABI_PushRegistersAndAdjustStack(BitSet32(ABI_ALL_CALLEE_SAVED & ABI_ALL_GPRS & ~BitSet32({RSP})), 8);
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MOV(64, R(RCPU), ImmPtr(cpu));
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@ -387,8 +385,8 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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for (int i = 0; i < instrsCount; i++)
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{
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R15 += Thumb ? 2 : 4;
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CurInstr = instrs[i];
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R15 = CurInstr.Addr + (Thumb ? 4 : 8);
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CompileFunc comp = Thumb
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? T_Comp[CurInstr.Info.Kind]
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@ -406,29 +404,21 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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}
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if (comp != NULL)
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RegCache.Prepare(i);
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RegCache.Prepare(Thumb, i);
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else
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RegCache.Flush();
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if (Thumb)
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{
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if (i < instrsCount - 1 && CurInstr.Info.Kind == ARMInstrInfo::tk_BL_LONG_1
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&& instrs[i + 1].Info.Kind == ARMInstrInfo::tk_BL_LONG_2)
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mergedThumbBL = true;
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else
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u32 icode = (CurInstr.Instr >> 6) & 0x3FF;
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if (comp == NULL)
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{
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u32 icode = (CurInstr.Instr >> 6) & 0x3FF;
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if (comp == NULL)
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{
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MOV(64, R(ABI_PARAM1), R(RCPU));
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MOV(64, R(ABI_PARAM1), R(RCPU));
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ABI_CallFunction(ARMInterpreter::THUMBInstrTable[icode]);
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}
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else if (mergedThumbBL)
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T_Comp_BL_Merged(instrs[i - 1]);
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else
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(this->*comp)();
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ABI_CallFunction(ARMInterpreter::THUMBInstrTable[icode]);
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}
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else
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(this->*comp)();
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}
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else
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{
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@ -90,7 +90,7 @@ public:
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void T_Comp_BranchXchangeReg();
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void T_Comp_BL_LONG_1();
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void T_Comp_BL_LONG_2();
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void T_Comp_BL_Merged(FetchedInstr prefix);
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void T_Comp_BL_Merged();
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void Comp_MemAccess(Gen::OpArg rd, bool signExtend, bool store, int size);
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s32 Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc, bool decrement, bool usermode);
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@ -212,6 +212,9 @@ enum
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tk_UNK,
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tk_SVC,
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// not a real instruction
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tk_BL_LONG,
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tk_Count
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};
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