From 048b0b8878f610a7e71b5e944614c498b12adb44 Mon Sep 17 00:00:00 2001
From: Jaklyy <102590697+Jaklyy@users.noreply.github.com>
Date: Mon, 10 Jun 2024 18:03:56 -0400
Subject: [PATCH] swp/swpb jumps work on the arm 7?

---
 src/ARMInterpreter_LoadStore.cpp | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/ARMInterpreter_LoadStore.cpp b/src/ARMInterpreter_LoadStore.cpp
index 2e841549..7a33b8dd 100644
--- a/src/ARMInterpreter_LoadStore.cpp
+++ b/src/ARMInterpreter_LoadStore.cpp
@@ -262,7 +262,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     if (r&1) { A_UNK(cpu); return; } \
     if (!cpu->DataRead32 (offset  , &cpu->R[r  ])) {cpu->AddCycles_CDI(); return;} \
     u32 val; if (!cpu->DataRead32S(offset+4, &val)) {cpu->AddCycles_CDI(); return;} \
-    if (r == 14) cpu->JumpTo(((((ARMv5*)cpu)->CP15Control & (1<<15)) ? (val & ~0x1) : val), cpu->CurInstr & (1<<22)); /* restores cpsr due to shared ldm dna */ \
+    if (r == 14) cpu->JumpTo(((((ARMv5*)cpu)->CP15Control & (1<<15)) ? (val & ~0x1) : val), cpu->CurInstr & (1<<22)); /* restores cpsr presumably due to shared dna with ldm */ \
     else cpu->R[r+1] = val; \
     cpu->AddCycles_CDI(); \
     if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset;
@@ -274,7 +274,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
     if (r&1) { A_UNK(cpu); return; } \
     if (!cpu->DataRead32 (addr  , &cpu->R[r  ])) {cpu->AddCycles_CDI(); return;} \
     u32 val; if (!cpu->DataRead32S(addr+4, &val)) {cpu->AddCycles_CDI(); return;} \
-    if (r == 14) cpu->JumpTo(((((ARMv5*)cpu)->CP15Control & (1<<15)) ? (val & ~0x1) : val), cpu->CurInstr & (1<<22)); /* restores cpsr due to shared ldm dna */ \
+    if (r == 14) cpu->JumpTo(((((ARMv5*)cpu)->CP15Control & (1<<15)) ? (val & ~0x1) : val), cpu->CurInstr & (1<<22)); /* restores cpsr presumably due to shared dna with ldm */ \
     else cpu->R[r+1] = val; \
     cpu->AddCycles_CDI(); \
     cpu->R[(cpu->CurInstr>>16) & 0xF] += offset;
@@ -408,9 +408,10 @@ void A_SWP(ARM* cpu)
         u32 numD = cpu->DataCycles;
         if (cpu->DataWrite32(base, rm))
         {
-            // rd only gets updated if both read and write succeed, and if rd isn't r15
+            // rd only gets updated if both read and write succeed
             u32 rd = (cpu->CurInstr >> 12) & 0xF;
             if (rd != 15) cpu->R[rd] = ROR(val, 8*(base&0x3));
+            else if (cpu->Num) cpu->JumpTo(ROR(val, 8*(base&0x3)) & ~1); // for some reason these jumps don't work on the arm 9?
         }
         cpu->DataCycles += numD;
     }
@@ -429,9 +430,10 @@ void A_SWPB(ARM* cpu)
         u32 numD = cpu->DataCycles;
         if (cpu->DataWrite8(base, rm))
         {
-            // rd only gets updated if both read and write succeed, and if rd isn't r15
+            // rd only gets updated if both read and write succeed
             u32 rd = (cpu->CurInstr >> 12) & 0xF;
             if (rd != 15) cpu->R[rd] = val;
+            else if (cpu->Num) cpu->JumpTo(val & ~1); // for some reason these jumps don't work on the arm 9?
         }
         cpu->DataCycles += numD;
     }