2016-11-24 17:31:49 +00:00
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#include <stdio.h>
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2016-11-03 00:38:58 +00:00
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#include "NDS.h"
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2016-11-24 17:31:49 +00:00
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#include "ARM.h"
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#include "ARMInterpreter.h"
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2016-11-03 00:38:58 +00:00
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2016-11-24 23:08:53 +00:00
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u32 ARM::ConditionTable[16] =
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{
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0xF0F0, // EQ
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0x0F0F, // NE
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0xCCCC, // CS
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0x3333, // CC
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0xFF00, // MI
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0x00FF, // PL
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0xAAAA, // VS
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0x5555, // VC
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0x0C0C, // HI
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0xF3F3, // LS
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0xAA55, // GE
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0x55AA, // LT
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0x0A05, // GT
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0xF5FA, // LE
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0xFFFF, // AL
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0x0000 // NE
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};
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2016-11-03 00:38:58 +00:00
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ARM::ARM(u32 num)
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{
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// well uh
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Num = num;
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2016-11-24 17:31:49 +00:00
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}
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ARM::~ARM()
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{
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// dorp
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}
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2016-11-03 00:38:58 +00:00
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2016-11-24 17:31:49 +00:00
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void ARM::Reset()
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{
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2016-11-03 00:38:58 +00:00
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for (int i = 0; i < 16; i++)
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R[i] = 0;
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2016-11-24 23:08:53 +00:00
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CPSR = 0x000000D3;
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2016-11-24 17:31:49 +00:00
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ExceptionBase = Num ? 0x00000000 : 0xFFFF0000;
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2016-11-03 00:38:58 +00:00
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// zorp
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JumpTo(ExceptionBase);
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}
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void ARM::JumpTo(u32 addr)
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{
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// pipeline shit
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2016-12-03 14:15:34 +00:00
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//printf("jump from %08X to %08X\n", R[15] - ((CPSR&0x20)?4:8), addr);
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2016-12-03 02:10:26 +00:00
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if (addr&1)
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{
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addr &= ~1;
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NextInstr = Read16(addr);
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R[15] = addr+2;
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CPSR |= 0x20;
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}
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else
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{
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addr &= ~3;
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NextInstr = Read32(addr);
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R[15] = addr+4;
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CPSR &= ~0x20;
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}
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2016-11-03 00:38:58 +00:00
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}
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2016-11-24 23:08:53 +00:00
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void ARM::RestoreCPSR()
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{
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printf("TODO: restore CPSR\n");
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}
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2016-12-03 03:41:10 +00:00
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void ARM::UpdateMode(u32 oldmode, u32 newmode)
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{
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u32 temp;
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#define SWAP(a, b) temp = a; a = b; b = temp;
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if ((oldmode & 0x1F) == (newmode & 0x1F)) return;
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switch (oldmode & 0x1F)
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{
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case 0x11:
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SWAP(R[8], R_FIQ[0]);
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SWAP(R[9], R_FIQ[1]);
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SWAP(R[10], R_FIQ[2]);
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SWAP(R[11], R_FIQ[3]);
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SWAP(R[12], R_FIQ[4]);
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SWAP(R[13], R_FIQ[5]);
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SWAP(R[14], R_FIQ[6]);
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break;
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case 0x12:
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SWAP(R[13], R_IRQ[0]);
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SWAP(R[14], R_IRQ[1]);
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break;
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case 0x13:
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SWAP(R[13], R_SVC[0]);
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SWAP(R[14], R_SVC[1]);
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break;
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case 0x17:
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SWAP(R[13], R_ABT[0]);
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SWAP(R[14], R_ABT[1]);
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break;
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case 0x1B:
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SWAP(R[13], R_UND[0]);
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SWAP(R[14], R_UND[1]);
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break;
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}
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switch (newmode & 0x1F)
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{
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case 0x11:
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SWAP(R[8], R_FIQ[0]);
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SWAP(R[9], R_FIQ[1]);
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SWAP(R[10], R_FIQ[2]);
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SWAP(R[11], R_FIQ[3]);
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SWAP(R[12], R_FIQ[4]);
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SWAP(R[13], R_FIQ[5]);
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SWAP(R[14], R_FIQ[6]);
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break;
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case 0x12:
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SWAP(R[13], R_IRQ[0]);
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SWAP(R[14], R_IRQ[1]);
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break;
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case 0x13:
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SWAP(R[13], R_SVC[0]);
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SWAP(R[14], R_SVC[1]);
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break;
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case 0x17:
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SWAP(R[13], R_ABT[0]);
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SWAP(R[14], R_ABT[1]);
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break;
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case 0x1B:
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SWAP(R[13], R_UND[0]);
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SWAP(R[14], R_UND[1]);
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break;
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}
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#undef SWAP
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}
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2016-11-03 00:38:58 +00:00
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s32 ARM::Execute(s32 cycles)
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{
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while (cycles > 0)
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{
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2016-12-03 02:10:26 +00:00
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if (CPSR & 0x20) // THUMB
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2016-11-24 23:08:53 +00:00
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{
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2016-12-03 02:10:26 +00:00
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// prefetch
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CurInstr = NextInstr;
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NextInstr = Read16(R[15]);
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R[15] += 2;
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// actually execute
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u32 icode = (CurInstr >> 6);
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cycles -= ARMInterpreter::THUMBInstrTable[icode](this);
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2016-11-24 23:08:53 +00:00
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}
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else
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{
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2016-12-03 02:10:26 +00:00
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// prefetch
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CurInstr = NextInstr;
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NextInstr = Read32(R[15]);
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R[15] += 4;
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// actually execute
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if (CheckCondition(CurInstr >> 28))
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{
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u32 icode = ((CurInstr >> 4) & 0xF) | ((CurInstr >> 16) & 0xFF0);
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cycles -= ARMInterpreter::ARMInstrTable[icode](this);
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}
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else if ((CurInstr & 0xFE000000) == 0xFA000000)
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{
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cycles -= ARMInterpreter::A_BLX_IMM(this);
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}
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else
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{
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// not executing it. oh well
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cycles -= 1; // 1S. todo: check
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}
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2016-11-24 23:08:53 +00:00
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}
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2016-11-03 00:38:58 +00:00
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}
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return cycles;
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}
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